Unverified Commit 0b84b662 authored Jul 23, 2019 by Philippe Mathieu-Daudé Committed by Palmer Dabbelt Sep 17, 2019

target/riscv/pmp: Restrict priviledged PMP to system-mode emulation



The RISC-V Physical Memory Protection is restricted to privileged
modes. Restrict its compilation to QEMU system builds.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

parent 04ece4f8

target/riscv/Makefile.objs

+2 −1

Original line number	Diff line number	Diff line
		obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o pmp.o
		obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o
		obj-$(CONFIG_SOFTMMU) += pmp.o

		DECODETREE = $(SRC_PATH)/scripts/decodetree.py

target/riscv/pmp.c

+0 −4

Original line number	Diff line number	Diff line
		@@ -28,8 +28,6 @@
		#include "qapi/error.h"
		#include "cpu.h"

		#ifndef CONFIG_USER_ONLY

		#define RISCV_DEBUG_PMP 0
		#define PMP_DEBUG(fmt, ...) \
		do { \
		@@ -382,5 +380,3 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
		return 0;
		}
		}

		#endif