Commit 6327c221 authored by Peter Crosthwaite's avatar Peter Crosthwaite Committed by Edgar E. Iglesias
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intc/xilinx_intc: Don't clear level sens. IRQs without ACK 



For level sensitive interrupts, ISR bits are cleared when the input pin
is lowered. This is incorrect. Only software can clear ISR bits (via
IAR or direct write to ISR with !MER(2)).

Signed-off-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@gmail.com>
parent 37a011e9

hw/intc/xilinx_intc.c

+1 −7
Original line number Diff line number Diff line
@@ -135,13 +135,7 @@ static void irq_handler(void *opaque, int irq, int level) 
        return;

    }



    /* Update source flops. Don't clear unless level triggered.

       Edge triggered interrupts only go away when explicitely acked to

       the interrupt controller.  */

    if (!(p->c_kind_of_intr & (1 << irq)) || level) {

        p->regs[R_ISR] &= ~(1 << irq);

    p->regs[R_ISR] |= (level << irq);

    }

    update_irq(p);

}