Commit 37a011e9 authored by Peter Crosthwaite's avatar Peter Crosthwaite Committed by Edgar E. Iglesias
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microblaze/petalogix_s3adsp1800_mmu: Fix UART IRQ 



The UART IRQ is edge sensitive, whereas the machine was registering it
as level sensitive. Fix.

Signed-off-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@gmail.com>
parent 21a885a7

hw/microblaze/petalogix_s3adsp1800_mmu.c

+1 −1
Original line number Diff line number Diff line
@@ -97,7 +97,7 @@ petalogix_s3adsp1800_init(QEMUMachineInitArgs *args) 
                          1, 0x89, 0x18, 0x0000, 0x0, 1);



    cpu_irq = microblaze_pic_init_cpu(env);

    dev = xilinx_intc_create(INTC_BASEADDR, cpu_irq[0], 2);

    dev = xilinx_intc_create(INTC_BASEADDR, cpu_irq[0], 0xA);

    for (i = 0; i < 32; i++) {

        irq[i] = qdev_get_gpio_in(dev, i);

    }