Commit 604e1f9c authored by Max Filippov's avatar Max Filippov
Browse files

target-xtensa: provide HW confg ID registers 



Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
parent 676056d4

target-xtensa/cpu.c

+2 −0
Original line number Diff line number Diff line
@@ -59,6 +59,8 @@ static void xtensa_cpu_reset(CPUState *s) 
    env->sregs[CACHEATTR] = 0x22222222;

    env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,

            XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;

    env->sregs[CONFIGID0] = env->config->configid[0];

    env->sregs[CONFIGID1] = env->config->configid[1];



    env->pending_irq_level = 0;

    reset_mmu(env);

target-xtensa/cpu.h

+4 −0
Original line number Diff line number Diff line
@@ -135,9 +135,11 @@ enum { 
    IBREAKA = 128,

    DBREAKA = 144,

    DBREAKC = 160,

    CONFIGID0 = 176,

    EPC1 = 177,

    DEPC = 192,

    EPS2 = 194,

    CONFIGID1 = 208,

    EXCSAVE1 = 209,

    CPENABLE = 224,

    INTSET = 226,
@@ -321,6 +323,8 @@ typedef struct XtensaConfig { 
    unsigned nibreak;

    unsigned ndbreak;



    uint32_t configid[2];



    uint32_t clock_freq_khz;



    xtensa_tlb itlb;

target-xtensa/overlay_tool.h

+8 −1
Original line number Diff line number Diff line
@@ -319,6 +319,12 @@ 
    .nibreak = XCHAL_NUM_IBREAK, \

    .ndbreak = XCHAL_NUM_DBREAK



#define CONFIG_SECTION \

    .configid = { \

        XCHAL_HW_CONFIGID0, \

        XCHAL_HW_CONFIGID1, \

    }



#define DEFAULT_SECTIONS \

    .options = XTENSA_OPTIONS, \

    .nareg = XCHAL_NUM_AREGS, \
@@ -326,7 +332,8 @@ 
    EXCEPTIONS_SECTION, \

    INTERRUPTS_SECTION, \

    TLB_SECTION, \

    DEBUG_SECTION

    DEBUG_SECTION, \

    CONFIG_SECTION





#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2

target-xtensa/translate.c

+7 −2
Original line number Diff line number Diff line
@@ -98,12 +98,15 @@ typedef struct XtensaReg { 


#define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)



#define XTENSA_REG_BITS(regname, opt) { \

#define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \

        .name = (regname), \

        .opt_bits = (opt), \

        .access = SR_RWX, \

        .access = (acc), \

    }



#define XTENSA_REG_BITS(regname, opt) \

    XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)



static const XtensaReg sregnames[256] = {

    [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),

    [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
@@ -134,6 +137,7 @@ static const XtensaReg sregnames[256] = { 
    [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),

    [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),

    [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),

    [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R),

    [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),

    [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),

    [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
@@ -148,6 +152,7 @@ static const XtensaReg sregnames[256] = { 
    [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),

    [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),

    [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),

    [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R),

    [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),

    [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",

            XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),