Commit 676056d4 authored by Max Filippov's avatar Max Filippov
Browse files

target-xtensa: refactor standard core configuration



Coalesce all standard configuration sections into single
DEFAULT_SECTIONS macro for all cores. This allows to add new features in
a single place: overlay_tool.h

Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
parent 2c09eee1
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+1 −7
Original line number Diff line number Diff line
@@ -35,7 +35,6 @@

static const XtensaConfig dc232b = {
    .name = "dc232b",
    .options = XTENSA_OPTIONS,
    .gdb_regmap = {
        .num_regs = 120,
        .num_core_regs = 52,
@@ -43,13 +42,8 @@ static const XtensaConfig dc232b = {
#include "core-dc232b/gdb-config.c"
        }
    },
    .nareg = XCHAL_NUM_AREGS,
    .ndepc = 1,
    EXCEPTIONS_SECTION,
    INTERRUPTS_SECTION,
    TLB_SECTION,
    DEBUG_SECTION,
    .clock_freq_khz = 10000,
    DEFAULT_SECTIONS
};

REGISTER_CORE(dc232b)
+1 −7
Original line number Diff line number Diff line
@@ -36,7 +36,6 @@

static const XtensaConfig dc233c = {
    .name = "dc233c",
    .options = XTENSA_OPTIONS,
    .gdb_regmap = {
        .num_regs = 121,
        .num_core_regs = 52,
@@ -44,13 +43,8 @@ static const XtensaConfig dc233c = {
#include "core-dc233c/gdb-config.c"
        }
    },
    .nareg = XCHAL_NUM_AREGS,
    .ndepc = 1,
    EXCEPTIONS_SECTION,
    INTERRUPTS_SECTION,
    TLB_SECTION,
    DEBUG_SECTION,
    .clock_freq_khz = 10000,
    DEFAULT_SECTIONS
};

REGISTER_CORE(dc233c)
+1 −7
Original line number Diff line number Diff line
@@ -35,15 +35,9 @@

static const XtensaConfig fsf = {
    .name = "fsf",
    .options = XTENSA_OPTIONS,
    /* GDB for this core is not supported currently */
    .nareg = XCHAL_NUM_AREGS,
    .ndepc = 1,
    EXCEPTIONS_SECTION,
    INTERRUPTS_SECTION,
    TLB_SECTION,
    DEBUG_SECTION,
    .clock_freq_khz = 10000,
    DEFAULT_SECTIONS
};

REGISTER_CORE(fsf)
+10 −0
Original line number Diff line number Diff line
@@ -319,6 +319,16 @@
    .nibreak = XCHAL_NUM_IBREAK, \
    .ndbreak = XCHAL_NUM_DBREAK

#define DEFAULT_SECTIONS \
    .options = XTENSA_OPTIONS, \
    .nareg = XCHAL_NUM_AREGS, \
    .ndepc = (XCHAL_XEA_VERSION >= 2), \
    EXCEPTIONS_SECTION, \
    INTERRUPTS_SECTION, \
    TLB_SECTION, \
    DEBUG_SECTION


#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0
#endif