Commit 5ef84f11 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Implement ARMv8.5-CondM 



Tested-by: default avatarLaurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190301200501.16533-9-richard.henderson@linaro.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent b89d9c98

target/arm/cpu.h

+5 −0
Original line number Diff line number Diff line
@@ -3436,6 +3436,11 @@ static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) 
    return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;

}



static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)

{

    return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;

}



static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)

{

    return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;

target/arm/cpu64.c

+1 −1
Original line number Diff line number Diff line
@@ -309,7 +309,7 @@ static void aarch64_max_initfn(Object *obj) 
        t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);

        t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);

        t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);

        t = FIELD_DP64(t, ID_AA64ISAR0, TS, 1);

        t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */

        cpu->isar.id_aa64isar0 = t;



        t = cpu->isar.id_aa64isar1;

target/arm/translate-a64.c

+58 −0
Original line number Diff line number Diff line
@@ -1646,6 +1646,48 @@ static void handle_sync(DisasContext *s, uint32_t insn, 
    }

}



static void gen_xaflag(void)

{

    TCGv_i32 z = tcg_temp_new_i32();



    tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0);



    /*

     * (!C & !Z) << 31

     * (!(C | Z)) << 31

     * ~((C | Z) << 31)

     * ~-(C | Z)

     * (C | Z) - 1

     */

    tcg_gen_or_i32(cpu_NF, cpu_CF, z);

    tcg_gen_subi_i32(cpu_NF, cpu_NF, 1);



    /* !(Z & C) */

    tcg_gen_and_i32(cpu_ZF, z, cpu_CF);

    tcg_gen_xori_i32(cpu_ZF, cpu_ZF, 1);



    /* (!C & Z) << 31 -> -(Z & ~C) */

    tcg_gen_andc_i32(cpu_VF, z, cpu_CF);

    tcg_gen_neg_i32(cpu_VF, cpu_VF);



    /* C | Z */

    tcg_gen_or_i32(cpu_CF, cpu_CF, z);



    tcg_temp_free_i32(z);

}



static void gen_axflag(void)

{

    tcg_gen_sari_i32(cpu_VF, cpu_VF, 31);         /* V ? -1 : 0 */

    tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF);     /* C & !V */



    /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */

    tcg_gen_andc_i32(cpu_ZF, cpu_ZF, cpu_VF);



    tcg_gen_movi_i32(cpu_NF, 0);

    tcg_gen_movi_i32(cpu_VF, 0);

}



/* MSR (immediate) - move immediate to processor state field */

static void handle_msr_i(DisasContext *s, uint32_t insn,

                         unsigned int op1, unsigned int op2, unsigned int crm)
@@ -1665,6 +1707,22 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, 
        s->base.is_jmp = DISAS_NEXT;

        break;



    case 0x01: /* XAFlag */

        if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {

            goto do_unallocated;

        }

        gen_xaflag();

        s->base.is_jmp = DISAS_NEXT;

        break;



    case 0x02: /* AXFlag */

        if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {

            goto do_unallocated;

        }

        gen_axflag();

        s->base.is_jmp = DISAS_NEXT;

        break;



    case 0x05: /* SPSel */

        if (s->current_el == 0) {

            goto do_unallocated;