Commit b89d9c98 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Implement ARMv8.4-CondM 



Tested-by: default avatarLaurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190301200501.16533-8-richard.henderson@linaro.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
[PMM: fixed up block comment style]
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 2fba34f7

linux-user/elfload.c

+1 −0
Original line number Diff line number Diff line
@@ -605,6 +605,7 @@ static uint32_t get_elf_hwcap(void) 
    GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM);

    GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT);

    GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB);

    GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM);



#undef GET_FEATURE_ID

target/arm/cpu.h

+5 −0
Original line number Diff line number Diff line
@@ -3431,6 +3431,11 @@ static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) 
    return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;

}



static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)

{

    return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;

}



static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)

{

    return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;

target/arm/cpu64.c

+1 −0
Original line number Diff line number Diff line
@@ -309,6 +309,7 @@ static void aarch64_max_initfn(Object *obj) 
        t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);

        t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);

        t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);

        t = FIELD_DP64(t, ID_AA64ISAR0, TS, 1);

        cpu->isar.id_aa64isar0 = t;



        t = cpu->isar.id_aa64isar1;

target/arm/translate-a64.c

+98 −1
Original line number Diff line number Diff line
@@ -1657,6 +1657,14 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, 
    s->base.is_jmp = DISAS_TOO_MANY;



    switch (op) {

    case 0x00: /* CFINV */

        if (crm != 0 || !dc_isar_feature(aa64_condm_4, s)) {

            goto do_unallocated;

        }

        tcg_gen_xori_i32(cpu_CF, cpu_CF, 1);

        s->base.is_jmp = DISAS_NEXT;

        break;



    case 0x05: /* SPSel */

        if (s->current_el == 0) {

            goto do_unallocated;
@@ -1710,7 +1718,6 @@ static void gen_get_nzcv(TCGv_i64 tcg_rt) 
}



static void gen_set_nzcv(TCGv_i64 tcg_rt)



{

    TCGv_i32 nzcv = tcg_temp_new_i32();
@@ -4529,6 +4536,84 @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn) 
    }

}



/*

 * Rotate right into flags

 *  31 30 29                21       15          10      5  4      0

 * +--+--+--+-----------------+--------+-----------+------+--+------+

 * |sf|op| S| 1 1 0 1 0 0 0 0 |  imm6  | 0 0 0 0 1 |  Rn  |o2| mask |

 * +--+--+--+-----------------+--------+-----------+------+--+------+

 */

static void disas_rotate_right_into_flags(DisasContext *s, uint32_t insn)

{

    int mask = extract32(insn, 0, 4);

    int o2 = extract32(insn, 4, 1);

    int rn = extract32(insn, 5, 5);

    int imm6 = extract32(insn, 15, 6);

    int sf_op_s = extract32(insn, 29, 3);

    TCGv_i64 tcg_rn;

    TCGv_i32 nzcv;



    if (sf_op_s != 5 || o2 != 0 || !dc_isar_feature(aa64_condm_4, s)) {

        unallocated_encoding(s);

        return;

    }



    tcg_rn = read_cpu_reg(s, rn, 1);

    tcg_gen_rotri_i64(tcg_rn, tcg_rn, imm6);



    nzcv = tcg_temp_new_i32();

    tcg_gen_extrl_i64_i32(nzcv, tcg_rn);



    if (mask & 8) { /* N */

        tcg_gen_shli_i32(cpu_NF, nzcv, 31 - 3);

    }

    if (mask & 4) { /* Z */

        tcg_gen_not_i32(cpu_ZF, nzcv);

        tcg_gen_andi_i32(cpu_ZF, cpu_ZF, 4);

    }

    if (mask & 2) { /* C */

        tcg_gen_extract_i32(cpu_CF, nzcv, 1, 1);

    }

    if (mask & 1) { /* V */

        tcg_gen_shli_i32(cpu_VF, nzcv, 31 - 0);

    }



    tcg_temp_free_i32(nzcv);

}



/*

 * Evaluate into flags

 *  31 30 29                21        15   14        10      5  4      0

 * +--+--+--+-----------------+---------+----+---------+------+--+------+

 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 |  Rn  |o3| mask |

 * +--+--+--+-----------------+---------+----+---------+------+--+------+

 */

static void disas_evaluate_into_flags(DisasContext *s, uint32_t insn)

{

    int o3_mask = extract32(insn, 0, 5);

    int rn = extract32(insn, 5, 5);

    int o2 = extract32(insn, 15, 6);

    int sz = extract32(insn, 14, 1);

    int sf_op_s = extract32(insn, 29, 3);

    TCGv_i32 tmp;

    int shift;



    if (sf_op_s != 1 || o2 != 0 || o3_mask != 0xd ||

        !dc_isar_feature(aa64_condm_4, s)) {

        unallocated_encoding(s);

        return;

    }

    shift = sz ? 16 : 24;  /* SETF16 or SETF8 */



    tmp = tcg_temp_new_i32();

    tcg_gen_extrl_i64_i32(tmp, cpu_reg(s, rn));

    tcg_gen_shli_i32(cpu_NF, tmp, shift);

    tcg_gen_shli_i32(cpu_VF, tmp, shift - 1);

    tcg_gen_mov_i32(cpu_ZF, cpu_NF);

    tcg_gen_xor_i32(cpu_VF, cpu_VF, cpu_NF);

    tcg_temp_free_i32(tmp);

}



/* Conditional compare (immediate / register)

 *  31 30 29 28 27 26 25 24 23 22 21  20    16 15  12  11  10  9   5  4 3   0

 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
@@ -5195,6 +5280,18 @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn) 
            disas_adc_sbc(s, insn);

            break;



        case 0x01: /* Rotate right into flags */

        case 0x21:

            disas_rotate_right_into_flags(s, insn);

            break;



        case 0x02: /* Evaluate into flags */

        case 0x12:

        case 0x22:

        case 0x32:

            disas_evaluate_into_flags(s, insn);

            break;



        default:

            goto do_unallocated;

        }