Commit 59e781fb authored by Stefan Markovic's avatar Stefan Markovic Committed by Aleksandar Markovic
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target/mips: Add availability control for DSP R3 ASE 



Add infrastructure for availability control for DSP R3 ASE MIPS
instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but
this is likely to be changed in near future.

Reviewed-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: default avatarStefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
parent 6208f094

target/mips/internal.h

+8 −3
Original line number Diff line number Diff line
@@ -307,8 +307,8 @@ static inline void compute_hflags(CPUMIPSState *env) 
    env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |

                     MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |

                     MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |

                     MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |

                     MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);

                     MIPS_HFLAG_DSPR3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |

                     MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);

    if (env->CP0_Status & (1 << CP0St_ERL)) {

        env->hflags |= MIPS_HFLAG_ERL;

    }
@@ -355,7 +355,12 @@ static inline void compute_hflags(CPUMIPSState *env) 
        (env->CP0_Config5 & (1 << CP0C5_SBRI))) {

        env->hflags |= MIPS_HFLAG_SBRI;

    }

    if (env->insn_flags & ASE_DSPR2) {

    if (env->insn_flags & ASE_DSPR3) {

        if (env->CP0_Status & (1 << CP0St_MX)) {

            env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |

                           MIPS_HFLAG_DSPR3;

        }

    } else if (env->insn_flags & ASE_DSPR2) {

        /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,

           so enable to access DSPR2 resources. */

        if (env->CP0_Status & (1 << CP0St_MX)) {

target/mips/translate.c

+12 −1
Original line number Diff line number Diff line
@@ -2407,6 +2407,17 @@ static inline void check_dspr2(DisasContext *ctx) 
    }

}









static inline void check_dspr3(DisasContext *ctx)









{









    if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR3))) {









        if (ctx->insn_flags & ASE_DSP) {









            generate_exception_end(ctx, EXCP_DSPDIS);









        } else {









            generate_exception_end(ctx, EXCP_RI);









        }









    }









}

















/* This code generates a "reserved instruction" exception if the









   CPU does not support the instruction set corresponding to flags. */









static inline void check_insn(DisasContext *ctx, uint64_t flags)








@@ -20637,7 +20648,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)







                    gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s);









                    break;









                case NM_BPOSGE32C:









                    check_dspr2(ctx);









                    check_dspr3(ctx);









                    {









                        int32_t imm = extract32(ctx->opcode, 1, 13) |









                                      extract32(ctx->opcode, 0, 1) << 13;

























target/mips/translate_init.inc.c



+2
−1






























Original line number
Diff line number
Diff line







@@ -485,7 +485,8 @@ const mips_def_t mips_defs[] =







        .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),









        .SEGBITS = 32,









        .PABITS = 32,









        .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_MT,









        .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 |









                      ASE_MT,









        .mmu_type = MMU_TYPE_R4000,









    },









#if defined(TARGET_MIPS64)