Unverified Commit 591bddea authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

RISC-V: Add support for the Zicsr extension 



The various CSR instructions have been split out of the base ISA as part
of the ratification process.  This patch adds a Zicsr argument, which
disables all the CSR instructions.

Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
parent 50fba816

target/riscv/cpu.c

+1 −0
Original line number Diff line number Diff line
@@ -442,6 +442,7 @@ static Property riscv_cpu_properties[] = { 
    DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),

    DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),

    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),

    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),

    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),

    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),

    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),

target/riscv/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -224,6 +224,7 @@ typedef struct RISCVCPU { 
        bool ext_u;

        bool ext_counters;

        bool ext_ifencei;

        bool ext_icsr;



        char *priv_spec;

        char *user_spec;

target/riscv/csr.c

+6 −0
Original line number Diff line number Diff line
@@ -793,6 +793,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 
{

    int ret;

    target_ulong old_value;

    RISCVCPU *cpu = env_archcpu(env);



    /* check privileges and return -1 if check fails */

#if !defined(CONFIG_USER_ONLY)
@@ -803,6 +804,11 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, 
    }

#endif



    /* ensure the CSR extension is enabled. */

    if (!cpu->cfg.ext_icsr) {

        return -1;

    }



    /* check predicate */

    if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {

        return -1;