Unverified Commit 50fba816 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

RISC-V: Add support for the Zifencei extension 



fence.i has been split out of the base ISA as part of the ratification
process.  This patch adds a Zifencei argument, which disables the
fence.i instruction.

Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@wdc.com>
parent 0a13a5b8

target/riscv/cpu.c

+1 −0
Original line number Diff line number Diff line
@@ -441,6 +441,7 @@ static Property riscv_cpu_properties[] = { 
    DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),

    DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),

    DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),

    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),

    DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),

    DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),

    DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),

target/riscv/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -223,6 +223,7 @@ typedef struct RISCVCPU { 
        bool ext_s;

        bool ext_u;

        bool ext_counters;

        bool ext_ifencei;



        char *priv_spec;

        char *user_spec;

target/riscv/insn_trans/trans_rvi.inc.c

+4 −0
Original line number Diff line number Diff line
@@ -484,6 +484,10 @@ static bool trans_fence(DisasContext *ctx, arg_fence *a) 


static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)

{

    if (!ctx->ext_ifencei) {

        return false;

    }



    /*

     * FENCE_I is a no-op in QEMU,

     * however we need to end the translation block

target/riscv/translate.c

+3 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ typedef struct DisasContext { 
       to any system register, which includes CSR_FRM, so we do not have

       to reset this known value.  */

    int frm;

    bool ext_ifencei;

} DisasContext;



#ifdef TARGET_RISCV64
@@ -752,6 +753,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 
{

    DisasContext *ctx = container_of(dcbase, DisasContext, base);

    CPURISCVState *env = cs->env_ptr;

    RISCVCPU *cpu = RISCV_CPU(cs);



    ctx->pc_succ_insn = ctx->base.pc_first;

    ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
@@ -759,6 +761,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 
    ctx->priv_ver = env->priv_ver;

    ctx->misa = env->misa;

    ctx->frm = -1;  /* unknown rounding mode */

    ctx->ext_ifencei = cpu->cfg.ext_ifencei;

}



static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)