Commit 5131dc43 authored by Robert Hoo's avatar Robert Hoo Committed by Eduardo Habkost
Browse files

i386: Add CPUID bit for PCONFIG 



PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0):
EDX[bit18].

Signed-off-by: default avatarRobert Hoo <robert.hu@linux.intel.com>
Message-Id: <1530781798-183214-4-git-send-email-robert.hu@linux.intel.com>
Signed-off-by: default avatarEduardo Habkost <ehabkost@redhat.com>
parent 3fc7c731

target/i386/cpu.c

+1 −1
Original line number Diff line number Diff line
@@ -997,7 +997,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 
            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, "pconfig", NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, "spec-ctrl", NULL,

            NULL, "arch-capabilities", NULL, "ssbd",

target/i386/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -689,6 +689,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 


#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */

#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */

#define CPUID_7_0_EDX_PCONFIG (1U << 18)       /* Platform Configuration */

#define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Speculation Control */

#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)  /*Arch Capabilities*/

#define CPUID_7_0_EDX_SPEC_CTRL_SSBD  (1U << 31) /* Speculative Store Bypass Disable */