Commit 3fc7c731 authored by Robert Hoo's avatar Robert Hoo Committed by Eduardo Habkost
Browse files

i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR 



Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
SPEC_CTRL.

At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable, per Paolo's
comment.

Signed-off-by: default avatarRobert Hoo <robert.hu@linux.intel.com>
Message-Id: <1530781798-183214-3-git-send-email-robert.hu@linux.intel.com>
Signed-off-by: default avatarEduardo Habkost <ehabkost@redhat.com>
parent 8c80c99f

target/i386/cpu.c

+2 −1
Original line number Diff line number Diff line
@@ -1000,12 +1000,13 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 
            NULL, NULL, NULL, NULL,

            NULL, NULL, NULL, NULL,

            NULL, NULL, "spec-ctrl", NULL,

            NULL, NULL, NULL, "ssbd",

            NULL, "arch-capabilities", NULL, "ssbd",

        },

        .cpuid_eax = 7,

        .cpuid_needs_ecx = true, .cpuid_ecx = 0,

        .cpuid_reg = R_EDX,

        .tcg_features = TCG_7_0_EDX_FEATURES,

        .unmigratable_flags = CPUID_7_0_EDX_ARCH_CAPABILITIES,

    },

    [FEAT_8000_0007_EDX] = {

        .feat_names = {

target/i386/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -690,6 +690,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */

#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */

#define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Speculation Control */

#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)  /*Arch Capabilities*/

#define CPUID_7_0_EDX_SPEC_CTRL_SSBD  (1U << 31) /* Speculative Store Bypass Disable */



#define CPUID_8000_0008_EBX_IBPB    (1U << 12) /* Indirect Branch Prediction Barrier */