Commit 5116c331 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/stefanberger/tags/pull-tpm-2018-02-21-2' into staging 



Merge tpm 2018/02/21 v2

# gpg: Signature made Tue 27 Feb 2018 13:50:28 GMT
# gpg:                using RSA key 75AD65802A0B4211
# gpg: Good signature from "Stefan Berger <stefanb@linux.vnet.ibm.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B818 B9CA DF90 89C2 D5CE  C66B 75AD 6580 2A0B 4211

* remotes/stefanberger/tags/pull-tpm-2018-02-21-2:
  tests: add test for TPM TIS device
  tests: Move common TPM test code into tpm-emu.c

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 66974397 adb0e917

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -1639,6 +1639,7 @@ F: include/hw/acpi/tpm.h 
F: include/sysemu/tpm*

F: qapi/tpm.json

F: backends/tpm.c

F: tests/*tpm*

T: git git://github.com/stefanberger/qemu-tpm.git tpm-next



Checkpatch

hw/tpm/tpm_tis.c

+0 −101
Original line number Diff line number Diff line
@@ -92,107 +92,6 @@ typedef struct TPMState { 
    } \

} while (0)



/* tis registers */

#define TPM_TIS_REG_ACCESS                0x00

#define TPM_TIS_REG_INT_ENABLE            0x08

#define TPM_TIS_REG_INT_VECTOR            0x0c

#define TPM_TIS_REG_INT_STATUS            0x10

#define TPM_TIS_REG_INTF_CAPABILITY       0x14

#define TPM_TIS_REG_STS                   0x18

#define TPM_TIS_REG_DATA_FIFO             0x24

#define TPM_TIS_REG_INTERFACE_ID          0x30

#define TPM_TIS_REG_DATA_XFIFO            0x80

#define TPM_TIS_REG_DATA_XFIFO_END        0xbc

#define TPM_TIS_REG_DID_VID               0xf00

#define TPM_TIS_REG_RID                   0xf04



/* vendor-specific registers */

#define TPM_TIS_REG_DEBUG                 0xf90



#define TPM_TIS_STS_TPM_FAMILY_MASK         (0x3 << 26)/* TPM 2.0 */

#define TPM_TIS_STS_TPM_FAMILY1_2           (0 << 26)  /* TPM 2.0 */

#define TPM_TIS_STS_TPM_FAMILY2_0           (1 << 26)  /* TPM 2.0 */

#define TPM_TIS_STS_RESET_ESTABLISHMENT_BIT (1 << 25)  /* TPM 2.0 */

#define TPM_TIS_STS_COMMAND_CANCEL          (1 << 24)  /* TPM 2.0 */



#define TPM_TIS_STS_VALID                 (1 << 7)

#define TPM_TIS_STS_COMMAND_READY         (1 << 6)

#define TPM_TIS_STS_TPM_GO                (1 << 5)

#define TPM_TIS_STS_DATA_AVAILABLE        (1 << 4)

#define TPM_TIS_STS_EXPECT                (1 << 3)

#define TPM_TIS_STS_SELFTEST_DONE         (1 << 2)

#define TPM_TIS_STS_RESPONSE_RETRY        (1 << 1)



#define TPM_TIS_BURST_COUNT_SHIFT         8

#define TPM_TIS_BURST_COUNT(X) \

    ((X) << TPM_TIS_BURST_COUNT_SHIFT)



#define TPM_TIS_ACCESS_TPM_REG_VALID_STS  (1 << 7)

#define TPM_TIS_ACCESS_ACTIVE_LOCALITY    (1 << 5)

#define TPM_TIS_ACCESS_BEEN_SEIZED        (1 << 4)

#define TPM_TIS_ACCESS_SEIZE              (1 << 3)

#define TPM_TIS_ACCESS_PENDING_REQUEST    (1 << 2)

#define TPM_TIS_ACCESS_REQUEST_USE        (1 << 1)

#define TPM_TIS_ACCESS_TPM_ESTABLISHMENT  (1 << 0)



#define TPM_TIS_INT_ENABLED               (1 << 31)

#define TPM_TIS_INT_DATA_AVAILABLE        (1 << 0)

#define TPM_TIS_INT_STS_VALID             (1 << 1)

#define TPM_TIS_INT_LOCALITY_CHANGED      (1 << 2)

#define TPM_TIS_INT_COMMAND_READY         (1 << 7)



#define TPM_TIS_INT_POLARITY_MASK         (3 << 3)

#define TPM_TIS_INT_POLARITY_LOW_LEVEL    (1 << 3)



#define TPM_TIS_INTERRUPTS_SUPPORTED (TPM_TIS_INT_LOCALITY_CHANGED | \

                                      TPM_TIS_INT_DATA_AVAILABLE   | \

                                      TPM_TIS_INT_STS_VALID | \

                                      TPM_TIS_INT_COMMAND_READY)



#define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28)

#define TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 (3 << 28)

#define TPM_TIS_CAP_DATA_TRANSFER_64B    (3 << 9)

#define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9)

#define TPM_TIS_CAP_BURST_COUNT_DYNAMIC  (0 << 8)

#define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL  (1 << 4) /* support is mandatory */

#define TPM_TIS_CAPABILITIES_SUPPORTED1_3 \

    (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \

     TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \

     TPM_TIS_CAP_DATA_TRANSFER_64B | \

     TPM_TIS_CAP_INTERFACE_VERSION1_3 | \

     TPM_TIS_INTERRUPTS_SUPPORTED)



#define TPM_TIS_CAPABILITIES_SUPPORTED2_0 \

    (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \

     TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \

     TPM_TIS_CAP_DATA_TRANSFER_64B | \

     TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 | \

     TPM_TIS_INTERRUPTS_SUPPORTED)



#define TPM_TIS_IFACE_ID_INTERFACE_TIS1_3   (0xf)     /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_INTERFACE_FIFO     (0x0)     /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO (0 << 4)  /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_CAP_5_LOCALITIES   (1 << 8)  /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED  (1 << 13) /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_INT_SEL_LOCK       (1 << 19) /* TPM 2.0 */



#define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS1_3 \

    (TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 | \

     (~0u << 4)/* all of it is don't care */)



/* if backend was a TPM 2.0: */

#define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS2_0 \

    (TPM_TIS_IFACE_ID_INTERFACE_FIFO | \

     TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO | \

     TPM_TIS_IFACE_ID_CAP_5_LOCALITIES | \

     TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED)



#define TPM_TIS_TPM_DID       0x0001

#define TPM_TIS_TPM_VID       PCI_VENDOR_ID_IBM

#define TPM_TIS_TPM_RID       0x0001



#define TPM_TIS_NO_DATA_BYTE  0xff



/* local prototypes */



static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr addr,

include/hw/acpi/tpm.h

+105 −0
Original line number Diff line number Diff line
@@ -23,6 +23,111 @@ 


#define TPM_TIS_IRQ                 5



#define TPM_TIS_NUM_LOCALITIES      5     /* per spec */

#define TPM_TIS_LOCALITY_SHIFT      12



/* tis registers */

#define TPM_TIS_REG_ACCESS                0x00

#define TPM_TIS_REG_INT_ENABLE            0x08

#define TPM_TIS_REG_INT_VECTOR            0x0c

#define TPM_TIS_REG_INT_STATUS            0x10

#define TPM_TIS_REG_INTF_CAPABILITY       0x14

#define TPM_TIS_REG_STS                   0x18

#define TPM_TIS_REG_DATA_FIFO             0x24

#define TPM_TIS_REG_INTERFACE_ID          0x30

#define TPM_TIS_REG_DATA_XFIFO            0x80

#define TPM_TIS_REG_DATA_XFIFO_END        0xbc

#define TPM_TIS_REG_DID_VID               0xf00

#define TPM_TIS_REG_RID                   0xf04



/* vendor-specific registers */

#define TPM_TIS_REG_DEBUG                 0xf90



#define TPM_TIS_STS_TPM_FAMILY_MASK         (0x3 << 26)/* TPM 2.0 */

#define TPM_TIS_STS_TPM_FAMILY1_2           (0 << 26)  /* TPM 2.0 */

#define TPM_TIS_STS_TPM_FAMILY2_0           (1 << 26)  /* TPM 2.0 */

#define TPM_TIS_STS_RESET_ESTABLISHMENT_BIT (1 << 25)  /* TPM 2.0 */

#define TPM_TIS_STS_COMMAND_CANCEL          (1 << 24)  /* TPM 2.0 */



#define TPM_TIS_STS_VALID                 (1 << 7)

#define TPM_TIS_STS_COMMAND_READY         (1 << 6)

#define TPM_TIS_STS_TPM_GO                (1 << 5)

#define TPM_TIS_STS_DATA_AVAILABLE        (1 << 4)

#define TPM_TIS_STS_EXPECT                (1 << 3)

#define TPM_TIS_STS_SELFTEST_DONE         (1 << 2)

#define TPM_TIS_STS_RESPONSE_RETRY        (1 << 1)



#define TPM_TIS_BURST_COUNT_SHIFT         8

#define TPM_TIS_BURST_COUNT(X) \

    ((X) << TPM_TIS_BURST_COUNT_SHIFT)



#define TPM_TIS_ACCESS_TPM_REG_VALID_STS  (1 << 7)

#define TPM_TIS_ACCESS_ACTIVE_LOCALITY    (1 << 5)

#define TPM_TIS_ACCESS_BEEN_SEIZED        (1 << 4)

#define TPM_TIS_ACCESS_SEIZE              (1 << 3)

#define TPM_TIS_ACCESS_PENDING_REQUEST    (1 << 2)

#define TPM_TIS_ACCESS_REQUEST_USE        (1 << 1)

#define TPM_TIS_ACCESS_TPM_ESTABLISHMENT  (1 << 0)



#define TPM_TIS_INT_ENABLED               (1 << 31)

#define TPM_TIS_INT_DATA_AVAILABLE        (1 << 0)

#define TPM_TIS_INT_STS_VALID             (1 << 1)

#define TPM_TIS_INT_LOCALITY_CHANGED      (1 << 2)

#define TPM_TIS_INT_COMMAND_READY         (1 << 7)



#define TPM_TIS_INT_POLARITY_MASK         (3 << 3)

#define TPM_TIS_INT_POLARITY_LOW_LEVEL    (1 << 3)



#define TPM_TIS_INTERRUPTS_SUPPORTED (TPM_TIS_INT_LOCALITY_CHANGED | \

                                      TPM_TIS_INT_DATA_AVAILABLE   | \

                                      TPM_TIS_INT_STS_VALID | \

                                      TPM_TIS_INT_COMMAND_READY)



#define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28)

#define TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 (3 << 28)

#define TPM_TIS_CAP_DATA_TRANSFER_64B    (3 << 9)

#define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9)

#define TPM_TIS_CAP_BURST_COUNT_DYNAMIC  (0 << 8)

#define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL  (1 << 4) /* support is mandatory */

#define TPM_TIS_CAPABILITIES_SUPPORTED1_3 \

    (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \

     TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \

     TPM_TIS_CAP_DATA_TRANSFER_64B | \

     TPM_TIS_CAP_INTERFACE_VERSION1_3 | \

     TPM_TIS_INTERRUPTS_SUPPORTED)



#define TPM_TIS_CAPABILITIES_SUPPORTED2_0 \

    (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \

     TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \

     TPM_TIS_CAP_DATA_TRANSFER_64B | \

     TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 | \

     TPM_TIS_INTERRUPTS_SUPPORTED)



#define TPM_TIS_IFACE_ID_INTERFACE_TIS1_3   (0xf)     /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_INTERFACE_FIFO     (0x0)     /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO (0 << 4)  /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_CAP_5_LOCALITIES   (1 << 8)  /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED  (1 << 13) /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_INT_SEL_LOCK       (1 << 19) /* TPM 2.0 */



#define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS1_3 \

    (TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 | \

     (~0u << 4)/* all of it is don't care */)



/* if backend was a TPM 2.0: */

#define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS2_0 \

    (TPM_TIS_IFACE_ID_INTERFACE_FIFO | \

     TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO | \

     TPM_TIS_IFACE_ID_CAP_5_LOCALITIES | \

     TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED)



#define TPM_TIS_TPM_DID       0x0001

#define TPM_TIS_TPM_VID       PCI_VENDOR_ID_IBM

#define TPM_TIS_TPM_RID       0x0001



#define TPM_TIS_NO_DATA_BYTE  0xff





REG32(CRB_LOC_STATE, 0x00)

  FIELD(CRB_LOC_STATE, tpmEstablished, 0, 1)

  FIELD(CRB_LOC_STATE, locAssigned, 1, 1)

tests/Makefile.include

+3 −1
Original line number Diff line number Diff line
@@ -287,6 +287,7 @@ ifeq ($(CONFIG_VHOST_USER_NET_TEST_i386),) 
check-qtest-x86_64-$(CONFIG_VHOST_USER_NET_TEST_x86_64) += tests/vhost-user-test$(EXESUF)

endif

check-qtest-i386-$(CONFIG_TPM) += tests/tpm-crb-test$(EXESUF)

check-qtest-i386-$(CONFIG_TPM) += tests/tpm-tis-test$(EXESUF)

check-qtest-i386-$(CONFIG_SLIRP) += tests/test-netfilter$(EXESUF)

check-qtest-i386-$(CONFIG_POSIX) += tests/test-filter-mirror$(EXESUF)

check-qtest-i386-$(CONFIG_POSIX) += tests/test-filter-redirector$(EXESUF)
@@ -714,7 +715,8 @@ tests/test-crypto-tlssession$(EXESUF): tests/test-crypto-tlssession.o \ 
tests/test-io-task$(EXESUF): tests/test-io-task.o $(test-io-obj-y)

tests/test-io-channel-socket$(EXESUF): tests/test-io-channel-socket.o \

        tests/io-channel-helpers.o $(test-io-obj-y)

tests/tpm-crb-test$(EXESUF): tests/tpm-crb-test.o $(test-io-obj-y)

tests/tpm-crb-test$(EXESUF): tests/tpm-crb-test.o tests/tpm-emu.o $(test-io-obj-y)

tests/tpm-tis-test$(EXESUF): tests/tpm-tis-test.o tests/tpm-emu.o $(test-io-obj-y)

tests/test-io-channel-file$(EXESUF): tests/test-io-channel-file.o \

        tests/io-channel-helpers.o $(test-io-obj-y)

tests/test-io-channel-tls$(EXESUF): tests/test-io-channel-tls.o \

tests/tpm-crb-test.c

+3 −171
Original line number Diff line number Diff line
@@ -14,177 +14,9 @@ 
#include <glib/gstdio.h>



#include "hw/acpi/tpm.h"

#include "hw/tpm/tpm_ioctl.h"

#include "io/channel-socket.h"

#include "libqtest.h"

#include "qapi/error.h"



#define TPM_RC_FAILURE 0x101

#define TPM2_ST_NO_SESSIONS 0x8001



struct tpm_hdr {

    uint16_t tag;

    uint32_t len;

    uint32_t code; /*ordinal/error */

    char buffer[];

} QEMU_PACKED;



typedef struct TestState {

    CompatGMutex data_mutex;

    CompatGCond data_cond;

    SocketAddress *addr;

    QIOChannel *tpm_ioc;

    GThread *emu_tpm_thread;

    struct tpm_hdr *tpm_msg;

} TestState;



static void test_wait_cond(TestState *s)

{

    gint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND;



    g_mutex_lock(&s->data_mutex);

    if (!g_cond_wait_until(&s->data_cond, &s->data_mutex, end_time)) {

        g_assert_not_reached();

    }

    g_mutex_unlock(&s->data_mutex);

}



static void *emu_tpm_thread(void *data)

{

    TestState *s = data;

    QIOChannel *ioc = s->tpm_ioc;



    s->tpm_msg = g_new(struct tpm_hdr, 1);

    while (true) {

        int minhlen = sizeof(s->tpm_msg->tag) + sizeof(s->tpm_msg->len);



        if (!qio_channel_read(ioc, (char *)s->tpm_msg, minhlen, &error_abort)) {

            break;

        }

        s->tpm_msg->tag = be16_to_cpu(s->tpm_msg->tag);

        s->tpm_msg->len = be32_to_cpu(s->tpm_msg->len);

        g_assert_cmpint(s->tpm_msg->len, >=, minhlen);

        g_assert_cmpint(s->tpm_msg->tag, ==, TPM2_ST_NO_SESSIONS);



        s->tpm_msg = g_realloc(s->tpm_msg, s->tpm_msg->len);

        qio_channel_read(ioc, (char *)&s->tpm_msg->code,

                         s->tpm_msg->len - minhlen, &error_abort);

        s->tpm_msg->code = be32_to_cpu(s->tpm_msg->code);



        /* reply error */

        s->tpm_msg->tag = cpu_to_be16(TPM2_ST_NO_SESSIONS);

        s->tpm_msg->len = cpu_to_be32(sizeof(struct tpm_hdr));

        s->tpm_msg->code = cpu_to_be32(TPM_RC_FAILURE);

        qio_channel_write(ioc, (char *)s->tpm_msg, be32_to_cpu(s->tpm_msg->len),

                          &error_abort);

    }



    g_free(s->tpm_msg);

    s->tpm_msg = NULL;

    object_unref(OBJECT(s->tpm_ioc));

    return NULL;

}



static void *emu_ctrl_thread(void *data)

{

    TestState *s = data;

    QIOChannelSocket *lioc = qio_channel_socket_new();

    QIOChannel *ioc;



    qio_channel_socket_listen_sync(lioc, s->addr, &error_abort);

    g_cond_signal(&s->data_cond);



    qio_channel_wait(QIO_CHANNEL(lioc), G_IO_IN);

    ioc = QIO_CHANNEL(qio_channel_socket_accept(lioc, &error_abort));

    g_assert(ioc);



    {

        uint32_t cmd = 0;

        struct iovec iov = { .iov_base = &cmd, .iov_len = sizeof(cmd) };

        int *pfd = NULL;

        size_t nfd = 0;



        qio_channel_readv_full(ioc, &iov, 1, &pfd, &nfd, &error_abort);

        cmd = be32_to_cpu(cmd);

        g_assert_cmpint(cmd, ==, CMD_SET_DATAFD);

        g_assert_cmpint(nfd, ==, 1);

        s->tpm_ioc = QIO_CHANNEL(qio_channel_socket_new_fd(*pfd, &error_abort));

        g_free(pfd);



        cmd = 0;

        qio_channel_write(ioc, (char *)&cmd, sizeof(cmd), &error_abort);



        s->emu_tpm_thread = g_thread_new(NULL, emu_tpm_thread, s);

    }



    while (true) {

        uint32_t cmd;

        ssize_t ret;



        ret = qio_channel_read(ioc, (char *)&cmd, sizeof(cmd), NULL);

        if (ret <= 0) {

            break;

        }



        cmd = be32_to_cpu(cmd);

        switch (cmd) {

        case CMD_GET_CAPABILITY: {

            ptm_cap cap = cpu_to_be64(0x3fff);

            qio_channel_write(ioc, (char *)&cap, sizeof(cap), &error_abort);

            break;

        }

        case CMD_INIT: {

            ptm_init init;

            qio_channel_read(ioc, (char *)&init.u.req, sizeof(init.u.req),

                              &error_abort);

            init.u.resp.tpm_result = 0;

            qio_channel_write(ioc, (char *)&init.u.resp, sizeof(init.u.resp),

                              &error_abort);

            break;

        }

        case CMD_SHUTDOWN: {

            ptm_res res = 0;

            qio_channel_write(ioc, (char *)&res, sizeof(res), &error_abort);

            qio_channel_close(s->tpm_ioc, &error_abort);

            g_thread_join(s->emu_tpm_thread);

            break;

        }

        case CMD_STOP: {

            ptm_res res = 0;

            qio_channel_write(ioc, (char *)&res, sizeof(res), &error_abort);

            break;

        }

        case CMD_SET_BUFFERSIZE: {

            ptm_setbuffersize sbs;

            qio_channel_read(ioc, (char *)&sbs.u.req, sizeof(sbs.u.req),

                             &error_abort);

            sbs.u.resp.buffersize = sbs.u.req.buffersize ?: cpu_to_be32(4096);

            sbs.u.resp.tpm_result = 0;

            sbs.u.resp.minsize = cpu_to_be32(128);

            sbs.u.resp.maxsize = cpu_to_be32(4096);

            qio_channel_write(ioc, (char *)&sbs.u.resp, sizeof(sbs.u.resp),

                              &error_abort);

            break;

        }

        case CMD_SET_LOCALITY: {

            ptm_loc loc;

            /* Note: this time it's not u.req / u.resp... */

            qio_channel_read(ioc, (char *)&loc, sizeof(loc), &error_abort);

            g_assert_cmpint(loc.u.req.loc, ==, 0);

            loc.u.resp.tpm_result = 0;

            qio_channel_write(ioc, (char *)&loc, sizeof(loc), &error_abort);

            break;

        }

        default:

            g_debug("unimplemented %u", cmd);

            g_assert_not_reached();

        }

    }



    object_unref(OBJECT(ioc));

    object_unref(OBJECT(lioc));

    return NULL;

}

#include "tpm-emu.h"



#define TPM_CMD "\x80\x01\x00\x00\x00\x0c\x00\x00\x01\x44\x00\x00"
@@ -250,8 +82,8 @@ int main(int argc, char **argv) 
    g_mutex_init(&test.data_mutex);

    g_cond_init(&test.data_cond);



    thread = g_thread_new(NULL, emu_ctrl_thread, &test);

    test_wait_cond(&test);

    thread = g_thread_new(NULL, tpm_emu_ctrl_thread, &test);

    tpm_emu_test_wait_cond(&test);



    args = g_strdup_printf(

        "-chardev socket,id=chr,path=%s "