Commit adb0e917 authored by Stefan Berger's avatar Stefan Berger
Browse files

tests: add test for TPM TIS device 



Move the TPM TIS related register and flag #defines into
include/hw/acpi/tpm.h for access by the test case.

Write a test case that covers the TIS functionality.

Add the tests cases to the MAINTAINERS file.

Signed-off-by: default avatarStefan Berger <stefanb@linux.vnet.ibm.com>
Reviewed-by: default avatarMarc-André Lureau <marcandre.lureau@redhat.com>
parent 0e6ca954

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -1633,6 +1633,7 @@ F: include/hw/acpi/tpm.h 
F: include/sysemu/tpm*

F: qapi/tpm.json

F: backends/tpm.c

F: tests/*tpm*

T: git git://github.com/stefanberger/qemu-tpm.git tpm-next



Checkpatch

hw/tpm/tpm_tis.c

+0 −101
Original line number Diff line number Diff line
@@ -92,107 +92,6 @@ typedef struct TPMState { 
    } \

} while (0)



/* tis registers */

#define TPM_TIS_REG_ACCESS                0x00

#define TPM_TIS_REG_INT_ENABLE            0x08

#define TPM_TIS_REG_INT_VECTOR            0x0c

#define TPM_TIS_REG_INT_STATUS            0x10

#define TPM_TIS_REG_INTF_CAPABILITY       0x14

#define TPM_TIS_REG_STS                   0x18

#define TPM_TIS_REG_DATA_FIFO             0x24

#define TPM_TIS_REG_INTERFACE_ID          0x30

#define TPM_TIS_REG_DATA_XFIFO            0x80

#define TPM_TIS_REG_DATA_XFIFO_END        0xbc

#define TPM_TIS_REG_DID_VID               0xf00

#define TPM_TIS_REG_RID                   0xf04



/* vendor-specific registers */

#define TPM_TIS_REG_DEBUG                 0xf90



#define TPM_TIS_STS_TPM_FAMILY_MASK         (0x3 << 26)/* TPM 2.0 */

#define TPM_TIS_STS_TPM_FAMILY1_2           (0 << 26)  /* TPM 2.0 */

#define TPM_TIS_STS_TPM_FAMILY2_0           (1 << 26)  /* TPM 2.0 */

#define TPM_TIS_STS_RESET_ESTABLISHMENT_BIT (1 << 25)  /* TPM 2.0 */

#define TPM_TIS_STS_COMMAND_CANCEL          (1 << 24)  /* TPM 2.0 */



#define TPM_TIS_STS_VALID                 (1 << 7)

#define TPM_TIS_STS_COMMAND_READY         (1 << 6)

#define TPM_TIS_STS_TPM_GO                (1 << 5)

#define TPM_TIS_STS_DATA_AVAILABLE        (1 << 4)

#define TPM_TIS_STS_EXPECT                (1 << 3)

#define TPM_TIS_STS_SELFTEST_DONE         (1 << 2)

#define TPM_TIS_STS_RESPONSE_RETRY        (1 << 1)



#define TPM_TIS_BURST_COUNT_SHIFT         8

#define TPM_TIS_BURST_COUNT(X) \

    ((X) << TPM_TIS_BURST_COUNT_SHIFT)



#define TPM_TIS_ACCESS_TPM_REG_VALID_STS  (1 << 7)

#define TPM_TIS_ACCESS_ACTIVE_LOCALITY    (1 << 5)

#define TPM_TIS_ACCESS_BEEN_SEIZED        (1 << 4)

#define TPM_TIS_ACCESS_SEIZE              (1 << 3)

#define TPM_TIS_ACCESS_PENDING_REQUEST    (1 << 2)

#define TPM_TIS_ACCESS_REQUEST_USE        (1 << 1)

#define TPM_TIS_ACCESS_TPM_ESTABLISHMENT  (1 << 0)



#define TPM_TIS_INT_ENABLED               (1 << 31)

#define TPM_TIS_INT_DATA_AVAILABLE        (1 << 0)

#define TPM_TIS_INT_STS_VALID             (1 << 1)

#define TPM_TIS_INT_LOCALITY_CHANGED      (1 << 2)

#define TPM_TIS_INT_COMMAND_READY         (1 << 7)



#define TPM_TIS_INT_POLARITY_MASK         (3 << 3)

#define TPM_TIS_INT_POLARITY_LOW_LEVEL    (1 << 3)



#define TPM_TIS_INTERRUPTS_SUPPORTED (TPM_TIS_INT_LOCALITY_CHANGED | \

                                      TPM_TIS_INT_DATA_AVAILABLE   | \

                                      TPM_TIS_INT_STS_VALID | \

                                      TPM_TIS_INT_COMMAND_READY)



#define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28)

#define TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 (3 << 28)

#define TPM_TIS_CAP_DATA_TRANSFER_64B    (3 << 9)

#define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9)

#define TPM_TIS_CAP_BURST_COUNT_DYNAMIC  (0 << 8)

#define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL  (1 << 4) /* support is mandatory */

#define TPM_TIS_CAPABILITIES_SUPPORTED1_3 \

    (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \

     TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \

     TPM_TIS_CAP_DATA_TRANSFER_64B | \

     TPM_TIS_CAP_INTERFACE_VERSION1_3 | \

     TPM_TIS_INTERRUPTS_SUPPORTED)



#define TPM_TIS_CAPABILITIES_SUPPORTED2_0 \

    (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \

     TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \

     TPM_TIS_CAP_DATA_TRANSFER_64B | \

     TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 | \

     TPM_TIS_INTERRUPTS_SUPPORTED)



#define TPM_TIS_IFACE_ID_INTERFACE_TIS1_3   (0xf)     /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_INTERFACE_FIFO     (0x0)     /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO (0 << 4)  /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_CAP_5_LOCALITIES   (1 << 8)  /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED  (1 << 13) /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_INT_SEL_LOCK       (1 << 19) /* TPM 2.0 */



#define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS1_3 \

    (TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 | \

     (~0u << 4)/* all of it is don't care */)



/* if backend was a TPM 2.0: */

#define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS2_0 \

    (TPM_TIS_IFACE_ID_INTERFACE_FIFO | \

     TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO | \

     TPM_TIS_IFACE_ID_CAP_5_LOCALITIES | \

     TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED)



#define TPM_TIS_TPM_DID       0x0001

#define TPM_TIS_TPM_VID       PCI_VENDOR_ID_IBM

#define TPM_TIS_TPM_RID       0x0001



#define TPM_TIS_NO_DATA_BYTE  0xff



/* local prototypes */



static uint64_t tpm_tis_mmio_read(void *opaque, hwaddr addr,

include/hw/acpi/tpm.h

+105 −0
Original line number Diff line number Diff line
@@ -23,6 +23,111 @@ 


#define TPM_TIS_IRQ                 5



#define TPM_TIS_NUM_LOCALITIES      5     /* per spec */

#define TPM_TIS_LOCALITY_SHIFT      12



/* tis registers */

#define TPM_TIS_REG_ACCESS                0x00

#define TPM_TIS_REG_INT_ENABLE            0x08

#define TPM_TIS_REG_INT_VECTOR            0x0c

#define TPM_TIS_REG_INT_STATUS            0x10

#define TPM_TIS_REG_INTF_CAPABILITY       0x14

#define TPM_TIS_REG_STS                   0x18

#define TPM_TIS_REG_DATA_FIFO             0x24

#define TPM_TIS_REG_INTERFACE_ID          0x30

#define TPM_TIS_REG_DATA_XFIFO            0x80

#define TPM_TIS_REG_DATA_XFIFO_END        0xbc

#define TPM_TIS_REG_DID_VID               0xf00

#define TPM_TIS_REG_RID                   0xf04



/* vendor-specific registers */

#define TPM_TIS_REG_DEBUG                 0xf90



#define TPM_TIS_STS_TPM_FAMILY_MASK         (0x3 << 26)/* TPM 2.0 */

#define TPM_TIS_STS_TPM_FAMILY1_2           (0 << 26)  /* TPM 2.0 */

#define TPM_TIS_STS_TPM_FAMILY2_0           (1 << 26)  /* TPM 2.0 */

#define TPM_TIS_STS_RESET_ESTABLISHMENT_BIT (1 << 25)  /* TPM 2.0 */

#define TPM_TIS_STS_COMMAND_CANCEL          (1 << 24)  /* TPM 2.0 */



#define TPM_TIS_STS_VALID                 (1 << 7)

#define TPM_TIS_STS_COMMAND_READY         (1 << 6)

#define TPM_TIS_STS_TPM_GO                (1 << 5)

#define TPM_TIS_STS_DATA_AVAILABLE        (1 << 4)

#define TPM_TIS_STS_EXPECT                (1 << 3)

#define TPM_TIS_STS_SELFTEST_DONE         (1 << 2)

#define TPM_TIS_STS_RESPONSE_RETRY        (1 << 1)



#define TPM_TIS_BURST_COUNT_SHIFT         8

#define TPM_TIS_BURST_COUNT(X) \

    ((X) << TPM_TIS_BURST_COUNT_SHIFT)



#define TPM_TIS_ACCESS_TPM_REG_VALID_STS  (1 << 7)

#define TPM_TIS_ACCESS_ACTIVE_LOCALITY    (1 << 5)

#define TPM_TIS_ACCESS_BEEN_SEIZED        (1 << 4)

#define TPM_TIS_ACCESS_SEIZE              (1 << 3)

#define TPM_TIS_ACCESS_PENDING_REQUEST    (1 << 2)

#define TPM_TIS_ACCESS_REQUEST_USE        (1 << 1)

#define TPM_TIS_ACCESS_TPM_ESTABLISHMENT  (1 << 0)



#define TPM_TIS_INT_ENABLED               (1 << 31)

#define TPM_TIS_INT_DATA_AVAILABLE        (1 << 0)

#define TPM_TIS_INT_STS_VALID             (1 << 1)

#define TPM_TIS_INT_LOCALITY_CHANGED      (1 << 2)

#define TPM_TIS_INT_COMMAND_READY         (1 << 7)



#define TPM_TIS_INT_POLARITY_MASK         (3 << 3)

#define TPM_TIS_INT_POLARITY_LOW_LEVEL    (1 << 3)



#define TPM_TIS_INTERRUPTS_SUPPORTED (TPM_TIS_INT_LOCALITY_CHANGED | \

                                      TPM_TIS_INT_DATA_AVAILABLE   | \

                                      TPM_TIS_INT_STS_VALID | \

                                      TPM_TIS_INT_COMMAND_READY)



#define TPM_TIS_CAP_INTERFACE_VERSION1_3 (2 << 28)

#define TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 (3 << 28)

#define TPM_TIS_CAP_DATA_TRANSFER_64B    (3 << 9)

#define TPM_TIS_CAP_DATA_TRANSFER_LEGACY (0 << 9)

#define TPM_TIS_CAP_BURST_COUNT_DYNAMIC  (0 << 8)

#define TPM_TIS_CAP_INTERRUPT_LOW_LEVEL  (1 << 4) /* support is mandatory */

#define TPM_TIS_CAPABILITIES_SUPPORTED1_3 \

    (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \

     TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \

     TPM_TIS_CAP_DATA_TRANSFER_64B | \

     TPM_TIS_CAP_INTERFACE_VERSION1_3 | \

     TPM_TIS_INTERRUPTS_SUPPORTED)



#define TPM_TIS_CAPABILITIES_SUPPORTED2_0 \

    (TPM_TIS_CAP_INTERRUPT_LOW_LEVEL | \

     TPM_TIS_CAP_BURST_COUNT_DYNAMIC | \

     TPM_TIS_CAP_DATA_TRANSFER_64B | \

     TPM_TIS_CAP_INTERFACE_VERSION1_3_FOR_TPM2_0 | \

     TPM_TIS_INTERRUPTS_SUPPORTED)



#define TPM_TIS_IFACE_ID_INTERFACE_TIS1_3   (0xf)     /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_INTERFACE_FIFO     (0x0)     /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO (0 << 4)  /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_CAP_5_LOCALITIES   (1 << 8)  /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED  (1 << 13) /* TPM 2.0 */

#define TPM_TIS_IFACE_ID_INT_SEL_LOCK       (1 << 19) /* TPM 2.0 */



#define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS1_3 \

    (TPM_TIS_IFACE_ID_INTERFACE_TIS1_3 | \

     (~0u << 4)/* all of it is don't care */)



/* if backend was a TPM 2.0: */

#define TPM_TIS_IFACE_ID_SUPPORTED_FLAGS2_0 \

    (TPM_TIS_IFACE_ID_INTERFACE_FIFO | \

     TPM_TIS_IFACE_ID_INTERFACE_VER_FIFO | \

     TPM_TIS_IFACE_ID_CAP_5_LOCALITIES | \

     TPM_TIS_IFACE_ID_CAP_TIS_SUPPORTED)



#define TPM_TIS_TPM_DID       0x0001

#define TPM_TIS_TPM_VID       PCI_VENDOR_ID_IBM

#define TPM_TIS_TPM_RID       0x0001



#define TPM_TIS_NO_DATA_BYTE  0xff





REG32(CRB_LOC_STATE, 0x00)

  FIELD(CRB_LOC_STATE, tpmEstablished, 0, 1)

  FIELD(CRB_LOC_STATE, locAssigned, 1, 1)

tests/Makefile.include

+2 −0
Original line number Diff line number Diff line
@@ -287,6 +287,7 @@ ifeq ($(CONFIG_VHOST_USER_NET_TEST_i386),) 
check-qtest-x86_64-$(CONFIG_VHOST_USER_NET_TEST_x86_64) += tests/vhost-user-test$(EXESUF)

endif

check-qtest-i386-$(CONFIG_TPM) += tests/tpm-crb-test$(EXESUF)

check-qtest-i386-$(CONFIG_TPM) += tests/tpm-tis-test$(EXESUF)

check-qtest-i386-$(CONFIG_SLIRP) += tests/test-netfilter$(EXESUF)

check-qtest-i386-$(CONFIG_POSIX) += tests/test-filter-mirror$(EXESUF)

check-qtest-i386-$(CONFIG_POSIX) += tests/test-filter-redirector$(EXESUF)
@@ -715,6 +716,7 @@ tests/test-io-task$(EXESUF): tests/test-io-task.o $(test-io-obj-y) 
tests/test-io-channel-socket$(EXESUF): tests/test-io-channel-socket.o \

        tests/io-channel-helpers.o $(test-io-obj-y)

tests/tpm-crb-test$(EXESUF): tests/tpm-crb-test.o tests/tpm-emu.o $(test-io-obj-y)

tests/tpm-tis-test$(EXESUF): tests/tpm-tis-test.o tests/tpm-emu.o $(test-io-obj-y)

tests/test-io-channel-file$(EXESUF): tests/test-io-channel-file.o \

        tests/io-channel-helpers.o $(test-io-obj-y)

tests/test-io-channel-tls$(EXESUF): tests/test-io-channel-tls.o \

tests/tpm-emu.c

+7 −0
Original line number Diff line number Diff line
@@ -155,6 +155,13 @@ void *tpm_emu_ctrl_thread(void *data) 
            qio_channel_write(ioc, (char *)&loc, sizeof(loc), &error_abort);

            break;

        }

        case CMD_GET_TPMESTABLISHED: {

            ptm_est est = {

                .u.resp.bit = 0,

            };

            qio_channel_write(ioc, (char *)&est, sizeof(est), &error_abort);

            break;

        }

        default:

            g_debug("unimplemented %u", cmd);

            g_assert_not_reached();