Commit 4f591025 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-oct-01-2019' into staging 



MIPS queue for October 1st, 2019

# gpg: Signature made Tue 01 Oct 2019 16:10:43 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-oct-01-2019:
  target/mips: msa: Move helpers for <AND|NOR|OR|XOR>.V
  target/mips: msa: Simplify and move helper for MOVE.V
  target/mips: msa: Split helpers for MOD_<S|U>.<B|H|W|D>
  target/mips: msa: Split helpers for DIV_<S|U>.<B|H|W|D>
  target/mips: msa: Split helpers for CLT_<S|U>.<B|H|W|D>
  target/mips: msa: Split helpers for CLE_<S|U>.<B|H|W|D>
  target/mips: msa: Split helpers for CEQ.<B|H|W|D>
  target/mips: msa: Split helpers for AVER_<S|U>.<B|H|W|D>
  target/mips: msa: Split helpers for AVE_<S|U>.<B|H|W|D>
  target/mips: msa: Split helpers for B<CLR|NEG|SEL>.<B|H|W|D>
  target/mips: msa: Unroll loops and demacro <BMNZ|BMZ|BSEL>.V
  target/mips: msa: Split helpers for BINS<L|R>.<B|H|W|D>
  target/mips: msa: Split helpers for PCNT.<B|H|W|D>
  target/mips: msa: Split helpers for <NLOC|NLZC>.<B|H|W|D>
  target/mips: Clean up translate.c
  target/mips: Clean up mips-defs.h
  target/mips: Clean up kvm_mips.h
  target/mips: Clean up internal.h

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 7f21573c 0a1bb912

target/mips/helper.h

+117 −27
Original line number Diff line number Diff line
@@ -777,6 +777,123 @@ DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) 
DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env)



/* MIPS SIMD Architecture */



DEF_HELPER_3(msa_nloc_b, void, env, i32, i32)

DEF_HELPER_3(msa_nloc_h, void, env, i32, i32)

DEF_HELPER_3(msa_nloc_w, void, env, i32, i32)

DEF_HELPER_3(msa_nloc_d, void, env, i32, i32)



DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32)

DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32)

DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32)

DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32)



DEF_HELPER_3(msa_pcnt_b, void, env, i32, i32)

DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32)

DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32)

DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32)



DEF_HELPER_4(msa_binsl_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_binsl_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_binsl_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_binsl_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_binsr_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32)

DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32)

DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32)



DEF_HELPER_4(msa_bclr_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_bclr_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_bclr_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_bclr_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_bneg_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_bneg_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_bneg_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_bneg_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_bset_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ave_s_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_ave_u_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ave_u_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ave_u_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ave_u_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_aver_s_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_aver_s_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_aver_s_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_aver_s_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_aver_u_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_aver_u_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_aver_u_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_aver_u_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_ceq_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ceq_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ceq_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ceq_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_cle_s_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_cle_s_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_cle_s_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_cle_s_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_cle_u_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_cle_u_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_cle_u_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_cle_u_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_clt_s_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_clt_s_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_clt_s_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_clt_s_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_clt_u_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_clt_u_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_clt_u_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_clt_u_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_div_s_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_div_s_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_div_s_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_div_s_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_div_u_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_mod_u_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_mod_s_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32)

DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32)

DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32)



DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32)

DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32)

DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32)

DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32)



DEF_HELPER_3(msa_move_v, void, env, i32, i32)



DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32)
@@ -815,9 +932,6 @@ DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32) 
DEF_HELPER_5(msa_sll_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_sra_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_srl_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_bclr_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_bset_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_bneg_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_addv_df, void, env, i32, i32, i32, i32)
@@ -828,19 +942,10 @@ DEF_HELPER_5(msa_min_s_df, void, env, i32, i32, i32, i32) 
DEF_HELPER_5(msa_min_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_max_a_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_min_a_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_ceq_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_clt_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_clt_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_cle_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_cle_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_adds_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_ave_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_ave_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_aver_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_aver_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_subs_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32)
@@ -850,10 +955,6 @@ DEF_HELPER_5(msa_asub_u_df, void, env, i32, i32, i32, i32) 
DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_maddv_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_div_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_div_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_mod_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_mod_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_dotp_s_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_dotp_u_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_dpadd_s_df, void, env, i32, i32, i32, i32)
@@ -882,7 +983,6 @@ DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32) 
DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32)

DEF_HELPER_3(msa_ctcmsa, void, env, tl, i32)

DEF_HELPER_2(msa_cfcmsa, tl, env, i32)

DEF_HELPER_3(msa_move_v, void, env, i32, i32)



DEF_HELPER_5(msa_fcaf_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_fcun_df, void, env, i32, i32, i32, i32)
@@ -926,17 +1026,7 @@ DEF_HELPER_5(msa_mulr_q_df, void, env, i32, i32, i32, i32) 
DEF_HELPER_5(msa_maddr_q_df, void, env, i32, i32, i32, i32)

DEF_HELPER_5(msa_msubr_q_df, void, env, i32, i32, i32, i32)



DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32)

DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32)

DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32)

DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32)

DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32)

DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32)

DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32)

DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32)

DEF_HELPER_4(msa_pcnt_df, void, env, i32, i32, i32)

DEF_HELPER_4(msa_nloc_df, void, env, i32, i32, i32)

DEF_HELPER_4(msa_nlzc_df, void, env, i32, i32, i32)



DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32)

DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32)

target/mips/internal.h

+37 −23
Original line number Diff line number Diff line 
/* mips internal definitions and helpers

/*

 * MIPS internal definitions and helpers

 *

 * This work is licensed under the terms of the GNU GPL, version 2 or later.

 * See the COPYING file in the top-level directory.
@@ -9,8 +10,10 @@ 


#include "fpu/softfloat-helpers.h"



/* MMU types, the first four entries have the same layout as the

   CP0C0_MT field.  */

/*

 * MMU types, the first four entries have the same layout as the

 * CP0C0_MT field.

 */

enum mips_mmu_types {

    MMU_TYPE_NONE,

    MMU_TYPE_R4000,
@@ -160,9 +163,11 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) 
        !(env->CP0_Status & (1 << CP0St_EXL)) &&

        !(env->CP0_Status & (1 << CP0St_ERL)) &&

        !(env->hflags & MIPS_HFLAG_DM) &&

        /* Note that the TCStatus IXMT field is initialized to zero,

           and only MT capable cores can set it to one. So we don't

           need to check for MT capabilities here.  */

        /*

         * Note that the TCStatus IXMT field is initialized to zero,

         * and only MT capable cores can set it to one. So we don't

         * need to check for MT capabilities here.

         */

        !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));

}
@@ -177,14 +182,18 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) 
    status = env->CP0_Status & CP0Ca_IP_mask;



    if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {

        /* A MIPS configured with a vectorizing external interrupt controller

           will feed a vector into the Cause pending lines. The core treats

           the status lines as a vector level, not as indiviual masks.  */

        /*

         * A MIPS configured with a vectorizing external interrupt controller

         * will feed a vector into the Cause pending lines. The core treats

         * the status lines as a vector level, not as indiviual masks.

         */

        r = pending > status;

    } else {

        /* A MIPS configured with compatibility or VInt (Vectored Interrupts)

           treats the pending lines as individual interrupt lines, the status

           lines are individual masks.  */

        /*

         * A MIPS configured with compatibility or VInt (Vectored Interrupts)

         * treats the pending lines as individual interrupt lines, the status

         * lines are individual masks.

         */

        r = (pending & status) != 0;

    }

    return r;
@@ -275,12 +284,14 @@ static inline int mips_vpe_active(CPUMIPSState *env) 
        active = 0;

    }



    /* Now verify that there are active thread contexts in the VPE.



       This assumes the CPU model will internally reschedule threads

       if the active one goes to sleep. If there are no threads available

       the active one will be in a sleeping state, and we can turn off

       the entire VPE.  */

    /*

     * Now verify that there are active thread contexts in the VPE.

     *

     * This assumes the CPU model will internally reschedule threads

     * if the active one goes to sleep. If there are no threads available

     * the active one will be in a sleeping state, and we can turn off

     * the entire VPE.

     */

    if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {

        /* TC is not activated.  */

        active = 0;
@@ -326,7 +337,8 @@ static inline void compute_hflags(CPUMIPSState *env) 
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&

        !(env->CP0_Status & (1 << CP0St_ERL)) &&

        !(env->hflags & MIPS_HFLAG_DM)) {

        env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;

        env->hflags |= (env->CP0_Status >> CP0St_KSU) &

                       MIPS_HFLAG_KSU;

    }

#if defined(TARGET_MIPS64)

    if ((env->insn_flags & ISA_MIPS3) &&
@@ -403,10 +415,12 @@ static inline void compute_hflags(CPUMIPSState *env) 
            env->hflags |= MIPS_HFLAG_COP1X;

        }

    } else if (env->insn_flags & ISA_MIPS4) {

        /* All supported MIPS IV CPUs use the XX (CU3) to enable

           and disable the MIPS IV extensions to the MIPS III ISA.

           Some other MIPS IV CPUs ignore the bit, so the check here

           would be too restrictive for them.  */

        /*

         * All supported MIPS IV CPUs use the XX (CU3) to enable

         * and disable the MIPS IV extensions to the MIPS III ISA.

         * Some other MIPS IV CPUs ignore the bit, so the check here

         * would be too restrictive for them.

         */

        if (env->CP0_Status & (1U << CP0St_CU3)) {

            env->hflags |= MIPS_HFLAG_COP1X;

        }

target/mips/mips-defs.h

+32 −26
Original line number Diff line number Diff line 
#ifndef QEMU_MIPS_DEFS_H

#define QEMU_MIPS_DEFS_H



/* If we want to use host float regs... */

//#define USE_HOST_FLOAT_REGS

/*

 * If we want to use host float regs...

 *

 * #define USE_HOST_FLOAT_REGS

 */



/* Real pages are variable size... */

#define MIPS_TLB_MAX 128
@@ -91,9 +94,12 @@ 
/* Wave Computing: "nanoMIPS" */

#define CPU_NANOMIPS32  (CPU_MIPS32R6 | ISA_NANOMIPS32)



/* Strictly follow the architecture standard:

   - Disallow "special" instruction handling for PMON/SPIM.

   Note that we still maintain Count/Compare to match the host clock. */

//#define MIPS_STRICT_STANDARD 1

/*

 * Strictly follow the architecture standard:

 * - Disallow "special" instruction handling for PMON/SPIM.

 * Note that we still maintain Count/Compare to match the host clock.

 *

 * #define MIPS_STRICT_STANDARD 1

 */



#endif /* QEMU_MIPS_DEFS_H */

target/mips/msa_helper.c

+1717 −446

File changed.

Preview size limit exceeded, changes collapsed.

target/mips/translate.c

+350 −71

File changed.

Preview size limit exceeded, changes collapsed.

target/mips/kvm_mips.h

+1 −1

File changed.

Contains only whitespace changes.