Commit 4b19de14 authored by Philippe Mathieu-Daudé's avatar Philippe Mathieu-Daudé
Browse files

hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers 



The IRQ Route Control registers definitions belong to the PIIX
chipset. We were only defining the 'A' register. Define the other
B, C and D registers, and use them.

Acked-by: default avatarPaul Durrant <paul@xen.org>
Reviewed-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: default avatarPhilippe Mathieu-Daudé <philmd@redhat.com>
parent 0063454a

hw/i386/xen/xen-hvm.c

+3 −2
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include "hw/pci/pci.h"

#include "hw/pci/pci_host.h"

#include "hw/i386/pc.h"

#include "hw/southbridge/piix.h"

#include "hw/irq.h"

#include "hw/hw.h"

#include "hw/i386/apic-msidef.h"
@@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len) 
            v = 0;

        }

        v &= 0xf;

        if (((address + i) >= 0x60) && ((address + i) <= 0x63)) {

            xen_set_pci_link_route(xen_domid, address + i - 0x60, v);

        if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {

            xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v);

        }

    }

}

hw/mips/gt64xxx_pci.c

+2 −2
Original line number Diff line number Diff line
@@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level) 


    /* now we change the pic irq level according to the piix irq mappings */

    /* XXX: optimize */

    pic_irq = piix4_dev->config[0x60 + irq_num];

    pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];

    if (pic_irq < 16) {

        /* The pic level is the logical OR of all the PCI irqs mapped to it. */

        pic_level = 0;

        for (i = 0; i < 4; i++) {

            if (pic_irq == piix4_dev->config[0x60 + i]) {

            if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {

                pic_level |= pci_irq_levels[i];

            }

        }

hw/pci-host/piix.c

+4 −5
Original line number Diff line number Diff line
@@ -61,7 +61,6 @@ typedef struct I440FXState { 
#define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */

#define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */

#define XEN_PIIX_NUM_PIRQS      128ULL

#define PIIX_PIRQC              0x60



typedef struct PIIX3State {

    PCIDevice dev;
@@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) 
    int pic_irq;

    uint64_t mask;



    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];

    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];

    if (pic_irq >= PIIX_NUM_PIC_IRQS) {

        return;

    }
@@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) 
{

    int pic_irq;



    pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];

    pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];

    if (pic_irq >= PIIX_NUM_PIC_IRQS) {

        return;

    }
@@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level) 
static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)

{

    PIIX3State *piix3 = opaque;

    int irq = piix3->dev.config[PIIX_PIRQC + pin];

    int irq = piix3->dev.config[PIIX_PIRQCA + pin];

    PCIINTxRoute route;



    if (irq < PIIX_NUM_PIC_IRQS) {
@@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev, 
                               uint32_t address, uint32_t val, int len)

{

    pci_default_write_config(dev, address, val, len);

    if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {

    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {

        PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);

        int pic_irq;

include/hw/southbridge/piix.h

+6 −0
Original line number Diff line number Diff line
@@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 
                      qemu_irq sci_irq, qemu_irq smi_irq,

                      int smm_enabled, DeviceState **piix4_pm);



/* PIRQRC[A:D]: PIRQx Route Control Registers */

#define PIIX_PIRQCA 0x60

#define PIIX_PIRQCB 0x61

#define PIIX_PIRQCC 0x62

#define PIIX_PIRQCD 0x63



/*

 * Reset Control Register: PCI-accessible ISA-Compatible Register at address

 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).