Commit 0063454a authored by Philippe Mathieu-Daudé's avatar Philippe Mathieu-Daudé Committed by Philippe Mathieu-Daudé
Browse files

hw/pci-host/piix: Move RCR_IOPORT register definition 



The RCR_IOPORT register belongs to the PIIX chipset.
Move the definition to "piix.h", and prepend the PIIX prefix.

Reviewed-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: default avatarPhilippe Mathieu-Daudé <philmd@redhat.com>
parent b7d255e1

hw/i386/acpi-build.c

+1 −1
Original line number Diff line number Diff line
@@ -209,7 +209,7 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) 


    /* The above need not be conditional on machine type because the reset port

     * happens to be the same on PIIX (pc) and ICH9 (q35). */

    QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);

    QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);



    /* Fill in optional s3/s4 related properties */

    o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);

hw/isa/piix4.c

+1 −1
Original line number Diff line number Diff line
@@ -166,7 +166,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) 
    memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,

                          "reset-control", 1);

    memory_region_add_subregion_overlap(pci_address_space_io(dev),

                                        RCR_IOPORT, &s->rcr_mem, 1);

                                        PIIX_RCR_IOPORT, &s->rcr_mem, 1);



    /* initialize i8259 pic */

    i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);

hw/pci-host/piix.c

+4 −3
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 
#include "hw/irq.h"

#include "hw/pci/pci.h"

#include "hw/pci/pci_host.h"

#include "hw/southbridge/piix.h"

#include "hw/qdev-properties.h"

#include "hw/isa/isa.h"

#include "hw/sysbus.h"
@@ -87,7 +88,7 @@ typedef struct PIIX3State { 
    /* Reset Control Register contents */

    uint8_t rcr;



    /* IO memory region for Reset Control Register (RCR_IOPORT) */

    /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */

    MemoryRegion rcr_mem;

} PIIX3State;
@@ -695,8 +696,8 @@ static void piix3_realize(PCIDevice *dev, Error **errp) 


    memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,

                          "piix3-reset-control", 1);

    memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,

                                        &d->rcr_mem, 1);

    memory_region_add_subregion_overlap(pci_address_space_io(dev),

                                        PIIX_RCR_IOPORT, &d->rcr_mem, 1);



    qemu_register_reset(piix3_reset, d);

}

include/hw/i386/pc.h

+0 −6
Original line number Diff line number Diff line
@@ -240,12 +240,6 @@ typedef struct PCII440FXState PCII440FXState; 


#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"



/*

 * Reset Control Register: PCI-accessible ISA-Compatible Register at address

 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).

 */

#define RCR_IOPORT 0xcf9



PCIBus *i440fx_init(const char *host_type, const char *pci_type,

                    PCII440FXState **pi440fx_state, int *piix_devfn,

                    ISABus **isa_bus, qemu_irq *pic,

include/hw/southbridge/piix.h

+6 −0
Original line number Diff line number Diff line
@@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 
                      qemu_irq sci_irq, qemu_irq smi_irq,

                      int smm_enabled, DeviceState **piix4_pm);



/*

 * Reset Control Register: PCI-accessible ISA-Compatible Register at address

 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).

 */

#define PIIX_RCR_IOPORT 0xcf9



extern PCIDevice *piix4_dev;



DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,