Commit 490aa7f1 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Enforce access to ZCR_EL at translation 



This also makes sure that we get the correct ordering of
SVE vs FP exceptions.

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180211205848.4568-5-richard.henderson@linaro.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent b916c9c3

target/arm/cpu.h

+2 −1
Original line number Diff line number Diff line
@@ -1750,10 +1750,11 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 
#define ARM_CP_DC_ZVA            (ARM_CP_SPECIAL | 0x0500)

#define ARM_LAST_SPECIAL         ARM_CP_DC_ZVA

#define ARM_CP_FPU               0x1000

#define ARM_CP_SVE               0x2000

/* Used only as a terminator for ARMCPRegInfo lists */

#define ARM_CP_SENTINEL          0xffff

/* Mask of only the flag bits in a type field */

#define ARM_CP_FLAG_MASK         0x10ff

#define ARM_CP_FLAG_MASK         0x30ff



/* Valid values for ARMCPRegInfo state field, indicating which of

 * the AArch32 and AArch64 execution states this register is visible in.

target/arm/helper.c

+4 −18
Original line number Diff line number Diff line
@@ -4335,20 +4335,6 @@ static int sve_exception_el(CPUARMState *env) 
    return 0;

}



static CPAccessResult zcr_access(CPUARMState *env, const ARMCPRegInfo *ri,

                                 bool isread)

{

    switch (sve_exception_el(env)) {

    case 3:

        return CP_ACCESS_TRAP_EL3;

    case 2:

        return CP_ACCESS_TRAP_EL2;

    case 1:

        return CP_ACCESS_TRAP;

    }

    return CP_ACCESS_OK;

}



static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,

                      uint64_t value)

{
@@ -4359,7 +4345,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, 
static const ARMCPRegInfo zcr_el1_reginfo = {

    .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,

    .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,

    .access = PL1_RW, .accessfn = zcr_access,

    .access = PL1_RW, .type = ARM_CP_SVE | ARM_CP_FPU,

    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),

    .writefn = zcr_write, .raw_writefn = raw_write

};
@@ -4367,7 +4353,7 @@ static const ARMCPRegInfo zcr_el1_reginfo = { 
static const ARMCPRegInfo zcr_el2_reginfo = {

    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,

    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,

    .access = PL2_RW, .accessfn = zcr_access,

    .access = PL2_RW, .type = ARM_CP_SVE | ARM_CP_FPU,

    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),

    .writefn = zcr_write, .raw_writefn = raw_write

};
@@ -4375,14 +4361,14 @@ static const ARMCPRegInfo zcr_el2_reginfo = { 
static const ARMCPRegInfo zcr_no_el2_reginfo = {

    .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,

    .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,

    .access = PL2_RW,

    .access = PL2_RW, .type = ARM_CP_SVE | ARM_CP_FPU,

    .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore

};



static const ARMCPRegInfo zcr_el3_reginfo = {

    .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,

    .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,

    .access = PL3_RW, .accessfn = zcr_access,

    .access = PL3_RW, .type = ARM_CP_SVE | ARM_CP_FPU,

    .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),

    .writefn = zcr_write, .raw_writefn = raw_write

};

target/arm/internals.h

+6 −0
Original line number Diff line number Diff line
@@ -243,6 +243,7 @@ enum arm_exception_class { 
    EC_AA64_HVC               = 0x16,

    EC_AA64_SMC               = 0x17,

    EC_SYSTEMREGISTERTRAP     = 0x18,

    EC_SVEACCESSTRAP          = 0x19,

    EC_INSNABORT              = 0x20,

    EC_INSNABORT_SAME_EL      = 0x21,

    EC_PCALIGNMENT            = 0x22,
@@ -381,6 +382,11 @@ static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit) 
        | (cv << 24) | (cond << 20);

}



static inline uint32_t syn_sve_access_trap(void)

{

    return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT;

}



static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)

{

    return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)

target/arm/translate-a64.c

+16 −0
Original line number Diff line number Diff line
@@ -1182,6 +1182,19 @@ static inline bool fp_access_check(DisasContext *s) 
    return false;

}



/* Check that SVE access is enabled.  If it is, return true.

 * If not, emit code to generate an appropriate exception and return false.

 */

static inline bool sve_access_check(DisasContext *s)

{

    if (s->sve_excp_el) {

        gen_exception_insn(s, 4, EXCP_UDEF, syn_sve_access_trap(),

                           s->sve_excp_el);

        return false;

    }

    return true;

}



/*

 * This utility function is for doing register extension with an

 * optional shift. You will likely want to pass a temporary for the
@@ -1631,6 +1644,9 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, 
    default:

        break;

    }

    if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {

        return;

    }

    if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {

        return;

    }