Commit b916c9c3 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Suppress TB end for FPCR/FPSR 



Nothing in either register affects the TB.

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180211205848.4568-4-richard.henderson@linaro.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent fe03d45f

target/arm/helper.c

+2 −2
Original line number Diff line number Diff line
@@ -3356,11 +3356,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { 
      .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },

    { .name = "FPCR", .state = ARM_CP_STATE_AA64,

      .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,

      .access = PL0_RW, .type = ARM_CP_FPU,

      .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END,

      .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },

    { .name = "FPSR", .state = ARM_CP_STATE_AA64,

      .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,

      .access = PL0_RW, .type = ARM_CP_FPU,

      .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END,

      .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },

    { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,

      .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,