Commit 47d3b608 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/riscv/tags/riscv-qemu-2.12-important-fixes' into staging 



RISC-V: Important fixes for QEMU 2.12

This series includes changes that are considered important.
i.e. correct user-visible bugs that are exercised by common
operations such as -cpu list (CPU model changes) or -d in_asm
(fix for disassembly of addiw)

# gpg: Signature made Wed 28 Mar 2018 21:34:57 BST
# gpg:                using DSA key 6BF1D7B357EF3E4F
# gpg: Good signature from "Michael Clark <michaeljclark@mac.com>"
# gpg:                 aka "Michael Clark <mjc@sifive.com>"
# gpg:                 aka "Michael Clark <michael@metaparadigm.com>"
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# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7C99 930E B17C D8BA 073D  5EFA 6BF1 D7B3 57EF 3E4F

* remotes/riscv/tags/riscv-qemu-2.12-important-fixes:
  RISC-V: Fix incorrect disassembly for addiw
  RISC-V: Convert cpu definition to future model

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 043289be 33b4f859

disas/riscv.c

+1 −1
Original line number Diff line number Diff line
@@ -600,7 +600,7 @@ static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end }; 
static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };

static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };

static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end };

static const rvc_constraint rvcc_sext_w[] = { rvc_rs2_eq_x0, rvc_end };

static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end };

static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end };

static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end };

static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end };

target/riscv/cpu.c

+69 −54
Original line number Diff line number Diff line
@@ -115,6 +115,8 @@ static void riscv_any_cpu_init(Object *obj) 
    set_resetvec(env, DEFAULT_RSTVEC);

}



#if defined(TARGET_RISCV32)



static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)

{

    CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -141,6 +143,8 @@ static void rv32imacu_nommu_cpu_init(Object *obj) 
    set_resetvec(env, DEFAULT_RSTVEC);

}



#elif defined(TARGET_RISCV64)



static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)

{

    CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -167,20 +171,7 @@ static void rv64imacu_nommu_cpu_init(Object *obj) 
    set_resetvec(env, DEFAULT_RSTVEC);

}



static const RISCVCPUInfo riscv_cpus[] = {

    { 96, TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init },

    { 32, TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init },

    { 32, TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init },

    { 32, TYPE_RISCV_CPU_RV32IMACU_NOMMU,  rv32imacu_nommu_cpu_init },

    { 32, TYPE_RISCV_CPU_SIFIVE_E31,       rv32imacu_nommu_cpu_init },

    { 32, TYPE_RISCV_CPU_SIFIVE_U34,       rv32gcsu_priv1_10_0_cpu_init },

    { 64, TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init },

    { 64, TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init },

    { 64, TYPE_RISCV_CPU_RV64IMACU_NOMMU,  rv64imacu_nommu_cpu_init },

    { 64, TYPE_RISCV_CPU_SIFIVE_E51,       rv64imacu_nommu_cpu_init },

    { 64, TYPE_RISCV_CPU_SIFIVE_U54,       rv64gcsu_priv1_10_0_cpu_init },

    { 0, NULL, NULL }

};

#endif



static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)

{
@@ -366,28 +357,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) 
    cc->vmsd = &vmstate_riscv_cpu;

}



static void cpu_register(const RISCVCPUInfo *info)

{

    TypeInfo type_info = {

        .name = info->name,

        .parent = TYPE_RISCV_CPU,

        .instance_size = sizeof(RISCVCPU),

        .instance_init = info->initfn,

    };



    type_register(&type_info);

}



static const TypeInfo riscv_cpu_type_info = {

    .name = TYPE_RISCV_CPU,

    .parent = TYPE_CPU,

    .instance_size = sizeof(RISCVCPU),

    .instance_init = riscv_cpu_init,

    .abstract = false,

    .class_size = sizeof(RISCVCPUClass),

    .class_init = riscv_cpu_class_init,

};



char *riscv_isa_string(RISCVCPU *cpu)

{

    int i;
@@ -403,30 +372,76 @@ char *riscv_isa_string(RISCVCPU *cpu) 
    return isa_str;

}



void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf)

typedef struct RISCVCPUListState {

    fprintf_function cpu_fprintf;

    FILE *file;

} RISCVCPUListState;



static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)

{

    const RISCVCPUInfo *info = riscv_cpus;

    ObjectClass *class_a = (ObjectClass *)a;

    ObjectClass *class_b = (ObjectClass *)b;

    const char *name_a, *name_b;



    while (info->name) {

        if (info->bit_widths & TARGET_LONG_BITS) {

            (*cpu_fprintf)(f, "%s\n", info->name);

        }

        info++;

    }

    name_a = object_class_get_name(class_a);

    name_b = object_class_get_name(class_b);

    return strcmp(name_a, name_b);

}



static void riscv_cpu_register_types(void)

static void riscv_cpu_list_entry(gpointer data, gpointer user_data)

{

    const RISCVCPUInfo *info = riscv_cpus;



    type_register_static(&riscv_cpu_type_info);

    RISCVCPUListState *s = user_data;

    const char *typename = object_class_get_name(OBJECT_CLASS(data));

    int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);



    while (info->name) {

        if (info->bit_widths & TARGET_LONG_BITS) {

            cpu_register(info);

    (*s->cpu_fprintf)(s->file, "%.*s\n", len, typename);

}

        info++;



void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf)

{

    RISCVCPUListState s = {

        .cpu_fprintf = cpu_fprintf,

        .file = f,

    };

    GSList *list;



    list = object_class_get_list(TYPE_RISCV_CPU, false);

    list = g_slist_sort(list, riscv_cpu_list_compare);

    g_slist_foreach(list, riscv_cpu_list_entry, &s);

    g_slist_free(list);

}



#define DEFINE_CPU(type_name, initfn)      \

    {                                      \

        .name = type_name,                 \

        .parent = TYPE_RISCV_CPU,          \

        .instance_init = initfn            \

    }



type_init(riscv_cpu_register_types)
 
static const TypeInfo riscv_cpu_type_infos[] = {

    {

        .name = TYPE_RISCV_CPU,

        .parent = TYPE_CPU,

        .instance_size = sizeof(RISCVCPU),

        .instance_init = riscv_cpu_init,

        .abstract = true,

        .class_size = sizeof(RISCVCPUClass),

        .class_init = riscv_cpu_class_init,

    },

    DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),

#if defined(TARGET_RISCV32)

    DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU,  rv32imacu_nommu_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32imacu_nommu_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32gcsu_priv1_10_0_cpu_init)

#elif defined(TARGET_RISCV64)

    DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU,  rv64imacu_nommu_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64imacu_nommu_cpu_init),

    DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64gcsu_priv1_10_0_cpu_init)

#endif

};



DEFINE_TYPES(riscv_cpu_type_infos)