Unverified Commit 33b4f859 authored by Michael Clark's avatar Michael Clark
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RISC-V: Fix incorrect disassembly for addiw 

This fixes a bug in the disassembler constraints used
to lift instructions into pseudo-instructions, whereby
addiw instructions are always lifted to sext.w instead
of just lifting addiw with a zero immediate.

An associated fix has been made to the metadata used to
machine generate the disseasembler:

https://github.com/michaeljclark/riscv-meta/


commit/4a6b2f3898430768acfe201405224d2ea31e1477

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarMichael Clark <mjc@sifive.com>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent eab15862

disas/riscv.c

+1 −1
Original line number Diff line number Diff line
@@ -600,7 +600,7 @@ static const rvc_constraint rvcc_mv[] = { rvc_imm_eq_zero, rvc_end }; 
static const rvc_constraint rvcc_not[] = { rvc_imm_eq_n1, rvc_end };

static const rvc_constraint rvcc_neg[] = { rvc_rs1_eq_x0, rvc_end };

static const rvc_constraint rvcc_negw[] = { rvc_rs1_eq_x0, rvc_end };

static const rvc_constraint rvcc_sext_w[] = { rvc_rs2_eq_x0, rvc_end };

static const rvc_constraint rvcc_sext_w[] = { rvc_imm_eq_zero, rvc_end };

static const rvc_constraint rvcc_seqz[] = { rvc_imm_eq_p1, rvc_end };

static const rvc_constraint rvcc_snez[] = { rvc_rs1_eq_x0, rvc_end };

static const rvc_constraint rvcc_sltz[] = { rvc_rs2_eq_x0, rvc_end };