Commit 47ba789c authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into staging 



qemu-sparc update

# gpg: Signature made Tue 31 Oct 2017 17:43:11 GMT
# gpg:                using RSA key 0x5BC2C56FAE0F321F
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>"
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C  C9C4 5BC2 C56F AE0F 321F

* remotes/mcayland/tags/qemu-sparc-signed:
  sun4m: change TYPE_SUN4M_IOMMU macro from "iommu" to "sun4m-iommu"
  sun4m_iommu: remove legacy sparc_iommu_memory_rw() function
  sparc32_dma: switch over to using IOMMU memory region and DMA API
  sun4m: implement IOMMU translation using IOMMU memory region
  sparc32_dma: add len to esp/le DMA memory tracing
  sparc32_dma: remove is_ledma hack and replace with memory region alias
  sparc32_dma: introduce new SPARC32_DMA type container object
  sparc32_dma: make lance device child of ledma device
  lance: move TYPE_LANCE and SysBusPCNetState from lance.c to lance.h
  sparc32_dma: make esp device child of espdma device
  esp: move TYPE_ESP and SysBusESPState from esp.c to esp.h
  sparc32_dma: use object link instead of qdev property to pass IOMMU reference
  sun4m_iommu: move TYPE_SUN4M_IOMMU declaration to sun4m.h
  sun4m: move DMA device wiring from sparc32_dma_init() to sun4m_hw_init()
  sparc32_dma: move type declarations from sparc32_dma.c to sparc32_dma.h
  sparc32_dma: split esp and le into separate DMA devices
  sparc32_dma: rename SPARC32_DMA type to SPARC32_DMA_DEVICE

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 7fa00e20 badd3d62

hw/dma/sparc32_dma.c

+185 −67
Original line number Diff line number Diff line
@@ -30,6 +30,8 @@ 
#include "hw/sparc/sparc32_dma.h"

#include "hw/sparc/sun4m.h"

#include "hw/sysbus.h"

#include "sysemu/dma.h"

#include "qapi/error.h"

#include "trace.h"



/*
@@ -40,7 +42,6 @@ 
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt

 */



#define DMA_REGS 4

#define DMA_SIZE (4 * sizeof(uint32_t))

/* We need the mask, because one instance of the device is not page

   aligned (ledma, start address 0x0010) */
@@ -61,22 +62,6 @@ 
/* XXX SCSI and ethernet should have different read-only bit masks */

#define DMA_CSR_RO_MASK 0xfe000007



#define TYPE_SPARC32_DMA "sparc32_dma"

#define SPARC32_DMA(obj) OBJECT_CHECK(DMAState, (obj), TYPE_SPARC32_DMA)



typedef struct DMAState DMAState;



struct DMAState {

    SysBusDevice parent_obj;



    MemoryRegion iomem;

    uint32_t dmaregs[DMA_REGS];

    qemu_irq irq;

    void *iommu;

    qemu_irq gpio[2];

    uint32_t is_ledma;

};



enum {

    GPIO_RESET = 0,

    GPIO_DMA,
@@ -86,17 +71,18 @@ enum { 
void ledma_memory_read(void *opaque, hwaddr addr,

                       uint8_t *buf, int len, int do_bswap)

{

    DMAState *s = opaque;

    DMADeviceState *s = opaque;

    IOMMUState *is = (IOMMUState *)s->iommu;

    int i;



    addr |= s->dmaregs[3];

    trace_ledma_memory_read(addr);

    trace_ledma_memory_read(addr, len);

    if (do_bswap) {

        sparc_iommu_memory_read(s->iommu, addr, buf, len);

        dma_memory_read(&is->iommu_as, addr, buf, len);

    } else {

        addr &= ~1;

        len &= ~1;

        sparc_iommu_memory_read(s->iommu, addr, buf, len);

        dma_memory_read(&is->iommu_as, addr, buf, len);

        for(i = 0; i < len; i += 2) {

            bswap16s((uint16_t *)(buf + i));

        }
@@ -106,14 +92,15 @@ void ledma_memory_read(void *opaque, hwaddr addr, 
void ledma_memory_write(void *opaque, hwaddr addr,

                        uint8_t *buf, int len, int do_bswap)

{

    DMAState *s = opaque;

    DMADeviceState *s = opaque;

    IOMMUState *is = (IOMMUState *)s->iommu;

    int l, i;

    uint16_t tmp_buf[32];



    addr |= s->dmaregs[3];

    trace_ledma_memory_write(addr);

    trace_ledma_memory_write(addr, len);

    if (do_bswap) {

        sparc_iommu_memory_write(s->iommu, addr, buf, len);

        dma_memory_write(&is->iommu_as, addr, buf, len);

    } else {

        addr &= ~1;

        len &= ~1;
@@ -124,7 +111,7 @@ void ledma_memory_write(void *opaque, hwaddr addr, 
            for(i = 0; i < l; i += 2) {

                tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));

            }

            sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l);

            dma_memory_write(&is->iommu_as, addr, tmp_buf, l);

            len -= l;

            buf += l;

            addr += l;
@@ -134,7 +121,7 @@ void ledma_memory_write(void *opaque, hwaddr addr, 


static void dma_set_irq(void *opaque, int irq, int level)

{

    DMAState *s = opaque;

    DMADeviceState *s = opaque;

    if (level) {

        s->dmaregs[0] |= DMA_INTR;

        if (s->dmaregs[0] & DMA_INTREN) {
@@ -154,34 +141,30 @@ static void dma_set_irq(void *opaque, int irq, int level) 


void espdma_memory_read(void *opaque, uint8_t *buf, int len)

{

    DMAState *s = opaque;

    DMADeviceState *s = opaque;

    IOMMUState *is = (IOMMUState *)s->iommu;



    trace_espdma_memory_read(s->dmaregs[1]);

    sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);

    trace_espdma_memory_read(s->dmaregs[1], len);

    dma_memory_read(&is->iommu_as, s->dmaregs[1], buf, len);

    s->dmaregs[1] += len;

}



void espdma_memory_write(void *opaque, uint8_t *buf, int len)

{

    DMAState *s = opaque;

    DMADeviceState *s = opaque;

    IOMMUState *is = (IOMMUState *)s->iommu;



    trace_espdma_memory_write(s->dmaregs[1]);

    sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);

    trace_espdma_memory_write(s->dmaregs[1], len);

    dma_memory_write(&is->iommu_as, s->dmaregs[1], buf, len);

    s->dmaregs[1] += len;

}



static uint64_t dma_mem_read(void *opaque, hwaddr addr,

                             unsigned size)

{

    DMAState *s = opaque;

    DMADeviceState *s = opaque;

    uint32_t saddr;



    if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) {

        /* aliased to espdma, but we can't get there from here */

        /* buggy driver if using undocumented behavior, just return 0 */

        trace_sparc32_dma_mem_readl(addr, 0);

        return 0;

    }

    saddr = (addr & DMA_MASK) >> 2;

    trace_sparc32_dma_mem_readl(addr, s->dmaregs[saddr]);

    return s->dmaregs[saddr];
@@ -190,14 +173,9 @@ static uint64_t dma_mem_read(void *opaque, hwaddr addr, 
static void dma_mem_write(void *opaque, hwaddr addr,

                          uint64_t val, unsigned size)

{

    DMAState *s = opaque;

    DMADeviceState *s = opaque;

    uint32_t saddr;



    if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) {

        /* aliased to espdma, but we can't get there from here */

        trace_sparc32_dma_mem_writel(addr, 0, val);

        return;

    }

    saddr = (addr & DMA_MASK) >> 2;

    trace_sparc32_dma_mem_writel(addr, s->dmaregs[saddr], val);

    switch (saddr) {
@@ -252,76 +230,216 @@ static const MemoryRegionOps dma_mem_ops = { 
    },

};



static void dma_reset(DeviceState *d)

static void sparc32_dma_device_reset(DeviceState *d)

{

    DMAState *s = SPARC32_DMA(d);

    DMADeviceState *s = SPARC32_DMA_DEVICE(d);



    memset(s->dmaregs, 0, DMA_SIZE);

    s->dmaregs[0] = DMA_VER;

}



static const VMStateDescription vmstate_dma = {

static const VMStateDescription vmstate_sparc32_dma_device = {

    .name ="sparc32_dma",

    .version_id = 2,

    .minimum_version_id = 2,

    .fields = (VMStateField[]) {

        VMSTATE_UINT32_ARRAY(dmaregs, DMAState, DMA_REGS),

        VMSTATE_UINT32_ARRAY(dmaregs, DMADeviceState, DMA_REGS),

        VMSTATE_END_OF_LIST()

    }

};



static void sparc32_dma_init(Object *obj)

static void sparc32_dma_device_init(Object *obj)

{

    DeviceState *dev = DEVICE(obj);

    DMAState *s = SPARC32_DMA(obj);

    DMADeviceState *s = SPARC32_DMA_DEVICE(obj);

    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);



    sysbus_init_irq(sbd, &s->irq);



    sysbus_init_mmio(sbd, &s->iomem);



    object_property_add_link(OBJECT(dev), "iommu", TYPE_SUN4M_IOMMU,

                             (Object **) &s->iommu,

                             qdev_prop_allow_set_link_before_realize,

                             0, NULL);



    qdev_init_gpio_in(dev, dma_set_irq, 1);

    qdev_init_gpio_out(dev, s->gpio, 2);

}



static void sparc32_dma_realize(DeviceState *dev, Error **errp)

static void sparc32_dma_device_class_init(ObjectClass *klass, void *data)

{

    DMAState *s = SPARC32_DMA(dev);

    int reg_size;

    DeviceClass *dc = DEVICE_CLASS(klass);



    reg_size = s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE;

    memory_region_init_io(&s->iomem, OBJECT(dev), &dma_mem_ops, s,

                          "dma", reg_size);

    dc->reset = sparc32_dma_device_reset;

    dc->vmsd = &vmstate_sparc32_dma_device;

}



static Property sparc32_dma_properties[] = {

    DEFINE_PROP_PTR("iommu_opaque", DMAState, iommu),

    DEFINE_PROP_UINT32("is_ledma", DMAState, is_ledma, 0),

    DEFINE_PROP_END_OF_LIST(),

static const TypeInfo sparc32_dma_device_info = {

    .name          = TYPE_SPARC32_DMA_DEVICE,

    .parent        = TYPE_SYS_BUS_DEVICE,

    .abstract      = true,

    .instance_size = sizeof(DMADeviceState),

    .instance_init = sparc32_dma_device_init,

    .class_init    = sparc32_dma_device_class_init,

};



static void sparc32_espdma_device_init(Object *obj)

{

    DMADeviceState *s = SPARC32_DMA_DEVICE(obj);



    memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,

                          "espdma-mmio", DMA_SIZE);

}



static void sparc32_espdma_device_realize(DeviceState *dev, Error **errp)

{

    DeviceState *d;

    SysBusESPState *sysbus;

    ESPState *esp;



    d = qdev_create(NULL, TYPE_ESP);

    object_property_add_child(OBJECT(dev), "esp", OBJECT(d), errp);

    sysbus = ESP_STATE(d);

    esp = &sysbus->esp;

    esp->dma_memory_read = espdma_memory_read;

    esp->dma_memory_write = espdma_memory_write;

    esp->dma_opaque = SPARC32_DMA_DEVICE(dev);

    sysbus->it_shift = 2;

    esp->dma_enabled = 1;

    qdev_init_nofail(d);

}



static void sparc32_espdma_device_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);



    dc->realize = sparc32_espdma_device_realize;

}



static const TypeInfo sparc32_espdma_device_info = {

    .name          = TYPE_SPARC32_ESPDMA_DEVICE,

    .parent        = TYPE_SPARC32_DMA_DEVICE,

    .instance_size = sizeof(ESPDMADeviceState),

    .instance_init = sparc32_espdma_device_init,

    .class_init    = sparc32_espdma_device_class_init,

};



static void sparc32_ledma_device_init(Object *obj)

{

    DMADeviceState *s = SPARC32_DMA_DEVICE(obj);



    memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,

                          "ledma-mmio", DMA_SIZE);

}



static void sparc32_ledma_device_realize(DeviceState *dev, Error **errp)

{

    DeviceState *d;

    NICInfo *nd = &nd_table[0];



    qemu_check_nic_model(nd, TYPE_LANCE);



    d = qdev_create(NULL, TYPE_LANCE);

    object_property_add_child(OBJECT(dev), "lance", OBJECT(d), errp);

    qdev_set_nic_properties(d, nd);

    qdev_prop_set_ptr(d, "dma", dev);

    qdev_init_nofail(d);

}



static void sparc32_ledma_device_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);



    dc->realize = sparc32_ledma_device_realize;

}



static const TypeInfo sparc32_ledma_device_info = {

    .name          = TYPE_SPARC32_LEDMA_DEVICE,

    .parent        = TYPE_SPARC32_DMA_DEVICE,

    .instance_size = sizeof(LEDMADeviceState),

    .instance_init = sparc32_ledma_device_init,

    .class_init    = sparc32_ledma_device_class_init,

};



static void sparc32_dma_realize(DeviceState *dev, Error **errp)

{

    SPARC32DMAState *s = SPARC32_DMA(dev);

    DeviceState *espdma, *esp, *ledma, *lance;

    SysBusDevice *sbd;

    Object *iommu;



    iommu = object_resolve_path_type("", TYPE_SUN4M_IOMMU, NULL);

    if (!iommu) {

        error_setg(errp, "unable to locate sun4m IOMMU device");

        return;

    }



    espdma = qdev_create(NULL, TYPE_SPARC32_ESPDMA_DEVICE);

    object_property_set_link(OBJECT(espdma), iommu, "iommu", errp);

    object_property_add_child(OBJECT(s), "espdma", OBJECT(espdma), errp);

    qdev_init_nofail(espdma);



    esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp"));

    sbd = SYS_BUS_DEVICE(esp);

    sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(espdma, 0));

    qdev_connect_gpio_out(espdma, 0, qdev_get_gpio_in(esp, 0));

    qdev_connect_gpio_out(espdma, 1, qdev_get_gpio_in(esp, 1));



    sbd = SYS_BUS_DEVICE(espdma);

    memory_region_add_subregion(&s->dmamem, 0x0,

                                sysbus_mmio_get_region(sbd, 0));



    ledma = qdev_create(NULL, TYPE_SPARC32_LEDMA_DEVICE);

    object_property_set_link(OBJECT(ledma), iommu, "iommu", errp);

    object_property_add_child(OBJECT(s), "ledma", OBJECT(ledma), errp);

    qdev_init_nofail(ledma);



    lance = DEVICE(object_resolve_path_component(OBJECT(ledma), "lance"));

    sbd = SYS_BUS_DEVICE(lance);

    sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(ledma, 0));

    qdev_connect_gpio_out(ledma, 0, qdev_get_gpio_in(lance, 0));



    sbd = SYS_BUS_DEVICE(ledma);

    memory_region_add_subregion(&s->dmamem, 0x10,

                                sysbus_mmio_get_region(sbd, 0));



    /* Add ledma alias to handle SunOS 5.7 - Solaris 9 invalid access bug */

    memory_region_init_alias(&s->ledma_alias, OBJECT(dev), "ledma-alias",

                             sysbus_mmio_get_region(sbd, 0), 0x4, 0x4);

    memory_region_add_subregion(&s->dmamem, 0x20, &s->ledma_alias);

}



static void sparc32_dma_init(Object *obj)

{

    SPARC32DMAState *s = SPARC32_DMA(obj);

    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);



    memory_region_init(&s->dmamem, OBJECT(s), "dma", DMA_SIZE + DMA_ETH_SIZE);

    sysbus_init_mmio(sbd, &s->dmamem);

}



static void sparc32_dma_class_init(ObjectClass *klass, void *data)

{

    DeviceClass *dc = DEVICE_CLASS(klass);



    dc->reset = dma_reset;

    dc->vmsd = &vmstate_dma;

    dc->props = sparc32_dma_properties;

    dc->realize = sparc32_dma_realize;

    /* Reason: pointer property "iommu_opaque" */

    dc->user_creatable = false;

}



static const TypeInfo sparc32_dma_info = {

    .name          = TYPE_SPARC32_DMA,

    .parent        = TYPE_SYS_BUS_DEVICE,

    .instance_size = sizeof(DMAState),

    .instance_size = sizeof(SPARC32DMAState),

    .instance_init = sparc32_dma_init,

    .class_init    = sparc32_dma_class_init,

};





static void sparc32_dma_register_types(void)

{

    type_register_static(&sparc32_dma_device_info);

    type_register_static(&sparc32_espdma_device_info);

    type_register_static(&sparc32_ledma_device_info);

    type_register_static(&sparc32_dma_info);

}

hw/dma/sun4m_iommu.c

+58 −43
Original line number Diff line number Diff line
@@ -36,7 +36,6 @@ 
 * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf

 */



#define IOMMU_NREGS         (4*4096/4)

#define IOMMU_CTRL          (0x0000 >> 2)

#define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */

#define IOMMU_CTRL_VERS     0x0f000000 /* Version */
@@ -128,19 +127,6 @@ 
#define IOMMU_PAGE_SIZE     (1 << IOMMU_PAGE_SHIFT)

#define IOMMU_PAGE_MASK     ~(IOMMU_PAGE_SIZE - 1)



#define TYPE_SUN4M_IOMMU "iommu"

#define SUN4M_IOMMU(obj) OBJECT_CHECK(IOMMUState, (obj), TYPE_SUN4M_IOMMU)



typedef struct IOMMUState {

    SysBusDevice parent_obj;



    MemoryRegion iomem;

    uint32_t regs[IOMMU_NREGS];

    hwaddr iostart;

    qemu_irq irq;

    uint32_t version;

} IOMMUState;



static uint64_t iommu_mem_read(void *opaque, hwaddr addr,

                               unsigned size)

{
@@ -292,37 +278,47 @@ static void iommu_bad_addr(IOMMUState *s, hwaddr addr, 
    qemu_irq_raise(s->irq);

}



void sparc_iommu_memory_rw(void *opaque, hwaddr addr,

                           uint8_t *buf, int len, int is_write)

/* Called from RCU critical section */

static IOMMUTLBEntry sun4m_translate_iommu(IOMMUMemoryRegion *iommu,

                                           hwaddr addr,

                                           IOMMUAccessFlags flags)

{

    int l;

    uint32_t flags;

    hwaddr page, phys_addr;

    IOMMUState *is = container_of(iommu, IOMMUState, iommu);

    hwaddr page, pa;

    int is_write = (flags & IOMMU_WO) ? 1 : 0;

    uint32_t pte;

    IOMMUTLBEntry ret = {

        .target_as = &address_space_memory,

        .iova = 0,

        .translated_addr = 0,

        .addr_mask = ~(hwaddr)0,

        .perm = IOMMU_NONE,

    };



    while (len > 0) {

    page = addr & IOMMU_PAGE_MASK;

        l = (page + IOMMU_PAGE_SIZE) - addr;

        if (l > len)

            l = len;

        flags = iommu_page_get_flags(opaque, page);

        if (!(flags & IOPTE_VALID)) {

            iommu_bad_addr(opaque, page, is_write);

            return;

    pte = iommu_page_get_flags(is, page);

    if (!(pte & IOPTE_VALID)) {

        iommu_bad_addr(is, page, is_write);

        return ret;

    }

        phys_addr = iommu_translate_pa(addr, flags);

        if (is_write) {

            if (!(flags & IOPTE_WRITE)) {

                iommu_bad_addr(opaque, page, is_write);

                return;



    pa = iommu_translate_pa(addr, pte);

    if (is_write && !(pte & IOPTE_WRITE)) {

        iommu_bad_addr(is, page, is_write);

        return ret;

    }

            cpu_physical_memory_write(phys_addr, buf, l);



    if (pte & IOPTE_WRITE) {

        ret.perm = IOMMU_RW;

    } else {

            cpu_physical_memory_read(phys_addr, buf, l);

        }

        len -= l;

        buf += l;

        addr += l;

        ret.perm = IOMMU_RO;

    }



    ret.iova = page;

    ret.translated_addr = pa;

    ret.addr_mask = ~IOMMU_PAGE_MASK;



    return ret;

}



static const VMStateDescription vmstate_iommu = {
@@ -354,6 +350,11 @@ static void iommu_init(Object *obj) 
    IOMMUState *s = SUN4M_IOMMU(obj);

    SysBusDevice *dev = SYS_BUS_DEVICE(obj);



    memory_region_init_iommu(&s->iommu, sizeof(s->iommu),

                             TYPE_SUN4M_IOMMU_MEMORY_REGION, OBJECT(dev),

                             "iommu-sun4m", UINT64_MAX);

    address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as");



    sysbus_init_irq(dev, &s->irq);



    memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu",
@@ -383,9 +384,23 @@ static const TypeInfo iommu_info = { 
    .class_init    = iommu_class_init,

};



static void sun4m_iommu_memory_region_class_init(ObjectClass *klass, void *data)

{

    IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);



    imrc->translate = sun4m_translate_iommu;

}



static const TypeInfo sun4m_iommu_memory_region_info = {

    .parent = TYPE_IOMMU_MEMORY_REGION,

    .name = TYPE_SUN4M_IOMMU_MEMORY_REGION,

    .class_init = sun4m_iommu_memory_region_class_init,

};



static void iommu_register_types(void)

{

    type_register_static(&iommu_info);

    type_register_static(&sun4m_iommu_memory_region_info);

}



type_init(iommu_register_types)

hw/dma/trace-events

+4 −4
Original line number Diff line number Diff line
@@ -7,12 +7,12 @@ rc4030_read(uint64_t addr, uint32_t ret) "read reg[0x%"PRIx64"] = 0x%x" 
rc4030_write(uint64_t addr, uint32_t val) "write reg[0x%"PRIx64"] = 0x%x"



# hw/dma/sparc32_dma.c

ledma_memory_read(uint64_t addr) "DMA read addr 0x%"PRIx64

ledma_memory_write(uint64_t addr) "DMA write addr 0x%"PRIx64

ledma_memory_read(uint64_t addr, int len) "DMA read addr 0x%"PRIx64 " len %d"

ledma_memory_write(uint64_t addr, int len) "DMA write addr 0x%"PRIx64 " len %d"

sparc32_dma_set_irq_raise(void) "Raise IRQ"

sparc32_dma_set_irq_lower(void) "Lower IRQ"

espdma_memory_read(uint32_t addr) "DMA read addr 0x%08x"

espdma_memory_write(uint32_t addr) "DMA write addr 0x%08x"

espdma_memory_read(uint32_t addr, int len) "DMA read addr 0x%08x len %d"

espdma_memory_write(uint32_t addr, int len) "DMA write addr 0x%08x len %d"

sparc32_dma_mem_readl(uint64_t addr, uint32_t ret) "read dmareg 0x%"PRIx64": 0x%08x"

sparc32_dma_mem_writel(uint64_t addr, uint32_t old, uint32_t val) "write dmareg 0x%"PRIx64": 0x%08x -> 0x%08x"

sparc32_dma_enable_raise(void) "Raise DMA enable"

hw/net/lance.c

+1 −10
Original line number Diff line number Diff line
@@ -41,19 +41,10 @@ 
#include "qemu/timer.h"

#include "qemu/sockets.h"

#include "hw/sparc/sun4m.h"

#include "pcnet.h"

#include "hw/net/lance.h"

#include "trace.h"

#include "sysemu/sysemu.h"



#define TYPE_LANCE "lance"

#define SYSBUS_PCNET(obj) \

    OBJECT_CHECK(SysBusPCNetState, (obj), TYPE_LANCE)



typedef struct {

    SysBusDevice parent_obj;



    PCNetState state;

} SysBusPCNetState;



static void parent_lance_reset(void *opaque, int irq, int level)

{

hw/scsi/esp.c

+0 −13
Original line number Diff line number Diff line
@@ -592,19 +592,6 @@ const VMStateDescription vmstate_esp = { 
    }

};



#define TYPE_ESP "esp"

#define ESP_STATE(obj) OBJECT_CHECK(SysBusESPState, (obj), TYPE_ESP)



typedef struct {

    /*< private >*/

    SysBusDevice parent_obj;

    /*< public >*/



    MemoryRegion iomem;

    uint32_t it_shift;

    ESPState esp;

} SysBusESPState;



static void sysbus_esp_mem_write(void *opaque, hwaddr addr,

                                 uint64_t val, unsigned int size)

{