Commit 7fa00e20 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20171031' into staging 



target-arm queue:
 * fix instruction-length bit in syndrome for WFI/WFE traps
 * xlnx-zcu102: Specify the max number of CPUs
 * msf2: Remove dead code reported by Coverity
 * msf2: Wire up SYSRESETREQ in SoC for system reset
 * hw/pci-host/gpex: Improve INTX to gsi routing error checking

# gpg: Signature made Tue 31 Oct 2017 13:10:02 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20171031:
  hw/pci-host/gpex: Improve INTX to gsi routing error checking
  msf2: Wire up SYSRESETREQ in SoC for system reset
  msf2: Remove dead code reported by Coverity
  xlnx-zcu102: Specify the max number of CPUs
  fix WFI/WFE length in syndrome register

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 92c7ec5c 168df2de

hw/arm/msf2-soc.c

+11 −0
Original line number Diff line number Diff line
@@ -57,6 +57,13 @@ static const int spi_irq[MSF2_NUM_SPIS] = { 2, 3 }; 
static const int uart_irq[MSF2_NUM_UARTS] = { 10, 11 };

static const int timer_irq[MSF2_NUM_TIMERS] = { 14, 15 };



static void do_sys_reset(void *opaque, int n, int level)

{

    if (level) {

        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);

    }

}



static void m2sxxx_soc_initfn(Object *obj)

{

    MSF2State *s = MSF2_SOC(obj);
@@ -125,6 +132,10 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) 
        error_append_hint(errp, "m3clk can not be zero\n");

        return;

    }



    qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0,

                                qemu_allocate_irq(&do_sys_reset, NULL, 0));



    system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk;



    for (i = 0; i < MSF2_NUM_UARTS; i++) {

hw/arm/xlnx-zcu102.c

+1 −0
Original line number Diff line number Diff line
@@ -240,6 +240,7 @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) 
    mc->block_default_type = IF_IDE;

    mc->units_per_default_bus = 1;

    mc->ignore_memory_transaction_failures = true;

    mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS;

}



static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {

hw/pci-host/gpex.c

+8 −2
Original line number Diff line number Diff line
@@ -57,9 +57,14 @@ static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin) 
{

    PCIINTxRoute route;

    GPEXHost *s = opaque;

    int gsi = s->irq_num[pin];



    route.irq = gsi;

    if (gsi < 0) {

        route.mode = PCI_INTX_DISABLED;

    } else {

        route.mode = PCI_INTX_ENABLED;

    route.irq = s->irq_num[pin];

    }



    return route;

}
@@ -81,6 +86,7 @@ static void gpex_host_realize(DeviceState *dev, Error **errp) 
    sysbus_init_mmio(sbd, &s->io_ioport);

    for (i = 0; i < GPEX_NUM_IRQS; i++) {

        sysbus_init_irq(sbd, &s->irq[i]);

        s->irq_num[i] = -1;

    }



    pci->bus = pci_register_bus(dev, "pcie.0", gpex_set_irq,

hw/ssi/mss-spi.c

+14 −4
Original line number Diff line number Diff line
@@ -76,9 +76,10 @@ 
#define C_BIGFIFO            (1 << 29)

#define C_RESET              (1 << 31)



#define FRAMESZ_MASK         0x1F

#define FRAMESZ_MASK         0x3F

#define FMCOUNT_MASK         0x00FFFF00

#define FMCOUNT_SHIFT        8

#define FRAMESZ_MAX          32



static void txfifo_reset(MSSSpiState *s)

{
@@ -104,10 +105,8 @@ static void set_fifodepth(MSSSpiState *s) 
        s->fifo_depth = 32;

    } else if (size <= 16) {

        s->fifo_depth = 16;

    } else if (size <= 32) {

        s->fifo_depth = 8;

    } else {

        s->fifo_depth = 4;

        s->fifo_depth = 8;

    }

}
@@ -301,6 +300,17 @@ static void spi_write(void *opaque, hwaddr addr, 
        if (s->enabled) {

            break;

        }

        /*

         * [31:6] bits are reserved bits and for future use.

         * [5:0] are for frame size. Only [5:0] bits are validated

         * during write, [31:6] bits are untouched.

         */

        if ((value & FRAMESZ_MASK) > FRAMESZ_MAX) {

            qemu_log_mask(LOG_GUEST_ERROR, "%s: Incorrect size %u provided."

                         "Maximum frame size is %u\n",

                         __func__, value & FRAMESZ_MASK, FRAMESZ_MAX);

            break;

        }

        s->regs[R_SPI_DFSIZE] = value;

        break;

target/arm/helper.h

+1 −1
Original line number Diff line number Diff line
@@ -48,7 +48,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, 
DEF_HELPER_2(exception_internal, void, env, i32)

DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32)

DEF_HELPER_1(setend, void, env)

DEF_HELPER_1(wfi, void, env)

DEF_HELPER_2(wfi, void, env, i32)

DEF_HELPER_1(wfe, void, env)

DEF_HELPER_1(yield, void, env)

DEF_HELPER_1(pre_hvc, void, env)