Commit 470dd165 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-09-2020' into staging 



MIPS queue for June 9th, 2020

# gpg: Signature made Tue 09 Jun 2020 17:18:59 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full]
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-jun-09-2020:
  target/mips: Enable hardware page table walker and CMGCR features for P5600
  target/mips: Add Loongson-3 CPU definition
  target/mips: fpu: Refactor conversion from ieee to mips exception flags
  target/mips: fpu: Name better paired-single variables
  target/mips: fpu: Remove now unused FLOAT_RINT macro
  target/mips: fpu: Demacro RINT.<D|S>
  target/mips: fpu: Remove now unused FLOAT_CLASS macro
  target/mips: fpu: Demacro CLASS.<D|S>
  target/mips: fpu: Remove now unused UNFUSED_FMA and FLOAT_FMA macros
  target/mips: fpu: Demacro NMSUB.<D|S|PS>
  target/mips: fpu: Demacro NMADD.<D|S|PS>
  target/mips: fpu: Demacro MSUB.<D|S|PS>
  target/mips: fpu: Demacro MADD.<D|S|PS>
  target/mips: fpu: Remove now unused macro FLOAT_BINOP
  target/mips: fpu: Demacro DIV.<D|S|PS>
  target/mips: fpu: Demacro MUL.<D|S|PS>
  target/mips: fpu: Demacro SUB.<D|S|PS>
  target/mips: fpu: Demacro ADD.<D|S|PS>
  mailmap: Change email address of Stefan Brankovic
  mailmap: Change email address of Filip Bozuta

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents c291aca6 6db06115

.mailmap

+2 −0
Original line number Diff line number Diff line
@@ -45,12 +45,14 @@ Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> <amarkovic@wavecomp.com> 
Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> <arikalo@wavecomp.com>

Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> <aleksandar.rikalo@rt-rk.com>

Anthony Liguori <anthony@codemonkey.ws> Anthony Liguori <aliguori@us.ibm.com>

Filip Bozuta <filip.bozuta@syrmia.com> <filip.bozuta@rt-rk.com.com>

James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>

Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>

Paul Burton <pburton@wavecomp.com> <paul.burton@mips.com>

Paul Burton <pburton@wavecomp.com> <paul.burton@imgtec.com>

Paul Burton <pburton@wavecomp.com> <paul@archlinuxmips.org>

Philippe Mathieu-Daudé <philmd@redhat.com> <f4bug@amsat.org>

Stefan Brankovic <stefan.brankovic@syrmia.com> <stefan.brankovic@rt-rk.com.com>

Yongbok Kim <yongbok.kim@mips.com> <yongbok.kim@imgtec.com>



# Also list preferred name forms where people have changed their

target/mips/Makefile.objs

+1 −1
Original line number Diff line number Diff line 
obj-y += translate.o cpu.o gdbstub.o helper.o

obj-y += op_helper.o cp0_helper.o fpu_helper.o

obj-y += dsp_helper.o lmi_helper.o msa_helper.o

obj-y += dsp_helper.o lmmi_helper.o msa_helper.o

obj-$(CONFIG_SOFTMMU) += mips-semi.o

obj-$(CONFIG_SOFTMMU) += machine.o cp0_timer.o

obj-$(CONFIG_KVM) += kvm.o

target/mips/cpu.h

+30 −2
Original line number Diff line number Diff line
@@ -198,8 +198,8 @@ typedef struct mips_def_t mips_def_t; 
 * 3   Config3                             WatchLo3          WatchHi

 * 4   Config4                             WatchLo4          WatchHi

 * 5   Config5                             WatchLo5          WatchHi

 * 6                                       WatchLo6          WatchHi

 * 7                                       WatchLo7          WatchHi

 * 6   Config6                             WatchLo6          WatchHi

 * 7   Config7                             WatchLo7          WatchHi

 *

 *

 *     Register 20       Register 21       Register 22       Register 23
@@ -940,7 +940,35 @@ struct CPUMIPSState { 
#define CP0C5_UFR          2

#define CP0C5_NFExists     0

    int32_t CP0_Config6;

    int32_t CP0_Config6_rw_bitmask;

#define CP0C6_BPPASS          31

#define CP0C6_KPOS            24

#define CP0C6_KE              23

#define CP0C6_VTLBONLY        22

#define CP0C6_LASX            21

#define CP0C6_SSEN            20

#define CP0C6_DISDRTIME       19

#define CP0C6_PIXNUEN         18

#define CP0C6_SCRAND          17

#define CP0C6_LLEXCEN         16

#define CP0C6_DISVC           15

#define CP0C6_VCLRU           14

#define CP0C6_DCLRU           13

#define CP0C6_PIXUEN          12

#define CP0C6_DISBLKLYEN      11

#define CP0C6_UMEMUALEN       10

#define CP0C6_SFBEN           8

#define CP0C6_FLTINT          7

#define CP0C6_VLTINT          6

#define CP0C6_DISBTB          5

#define CP0C6_STPREFCTL       2

#define CP0C6_INSTPREF        1

#define CP0C6_DATAPREF        0

    int32_t CP0_Config7;

    int64_t CP0_Config7_rw_bitmask;

#define CP0C7_NAPCGEN       2

#define CP0C7_UNIMUEN       1

#define CP0C7_VFPUCGEN      0

    uint64_t CP0_LLAddr;

    uint64_t CP0_MAAR[MIPS_MAAR_MAX];

    int32_t CP0_MAARI;

target/mips/fpu_helper.c

+453 −205

File changed.

Preview size limit exceeded, changes collapsed.

target/mips/internal.h

+2 −1
Original line number Diff line number Diff line
@@ -36,7 +36,9 @@ struct mips_def_t { 
    int32_t CP0_Config5;

    int32_t CP0_Config5_rw_bitmask;

    int32_t CP0_Config6;

    int32_t CP0_Config6_rw_bitmask;

    int32_t CP0_Config7;

    int32_t CP0_Config7_rw_bitmask;

    target_ulong CP0_LLAddr_rw_bitmask;

    int CP0_LLAddr_shift;

    int32_t SYNCI_Step;
@@ -224,7 +226,6 @@ uint32_t float_class_s(uint32_t arg, float_status *fst); 
uint64_t float_class_d(uint64_t arg, float_status *fst);



extern unsigned int ieee_rm[];

int ieee_ex_to_mips(int xcpt);

void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);



static inline void restore_rounding_mode(CPUMIPSState *env)