Commit 4700a316 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

pc: port 92 reset requires a low->high transition 



The PIIX datasheet says that "before another INIT pulse can be
generated via [port 92h], [bit 0] must be written back to a
zero.

This bug is masked right now because a full reset will clear the
value of port 92h.  But once we implement soft reset correctly,
the next attempt to enable the A20 line by setting bit 1 (and
leaving the others untouched) will cause another reset.

Reviewed-by: default avatarAnthony Liguori <aliguori@us.ibm.com>
Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 4a92a558

hw/i386/pc.c

+2 −1
Original line number Diff line number Diff line
@@ -471,11 +471,12 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val, 
                         unsigned size)

{

    Port92State *s = opaque;

    int oldval = s->outport;



    DPRINTF("port92: write 0x%02x\n", val);

    s->outport = val;

    qemu_set_irq(*s->a20_out, (val >> 1) & 1);

    if (val & 1) {

    if ((val & 1) && !(oldval & 1)) {

        qemu_system_reset_request();

    }

}