Commit 4a92a558 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

cpu: make CPU_INTERRUPT_RESET available on all targets 



On the x86, some devices need access to the CPU reset pin (INIT#).
Provide a generic service to do this, using one of the internal
cpu_interrupt targets.  Generalize the PPC-specific code for
CPU_INTERRUPT_RESET to other targets.

Since PPC does not support migration across QEMU versions (its
machine types are not versioned yet), I picked the value that
is used on x86, CPU_INTERRUPT_TGT_INT_1.  Consequently, TGT_INT_2
and TGT_INT_3 are shifted down by one while keeping their value.

Reviewed-by: default avatarAnthony Liguori <aliguori@us.ibm.com>
Reviewed-by: default avatarMichael S. Tsirkin <mst@redhat.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 7b4d915e

cpu-exec.c

+13 −10
Original line number Diff line number Diff line
@@ -335,6 +335,18 @@ int cpu_exec(CPUArchState *env) 
                        cpu_loop_exit(cpu);

                    }

#endif

#if defined(TARGET_I386)

                    if (interrupt_request & CPU_INTERRUPT_INIT) {

                        cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0);

                        do_cpu_init(x86_cpu);

                        cpu->exception_index = EXCP_HALTED;

                        cpu_loop_exit(cpu);

                    }

#else

                    if (interrupt_request & CPU_INTERRUPT_RESET) {

                        cpu_reset(cpu);

                    }

#endif

#if defined(TARGET_I386)

#if !defined(CONFIG_USER_ONLY)

                    if (interrupt_request & CPU_INTERRUPT_POLL) {
@@ -342,13 +354,7 @@ int cpu_exec(CPUArchState *env) 
                        apic_poll_irq(x86_cpu->apic_state);

                    }

#endif

                    if (interrupt_request & CPU_INTERRUPT_INIT) {

                            cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,

                                                          0);

                            do_cpu_init(x86_cpu);

                            cpu->exception_index = EXCP_HALTED;

                            cpu_loop_exit(cpu);

                    } else if (interrupt_request & CPU_INTERRUPT_SIPI) {

                    if (interrupt_request & CPU_INTERRUPT_SIPI) {

                            do_cpu_sipi(x86_cpu);

                    } else if (env->hflags2 & HF2_GIF_MASK) {

                        if ((interrupt_request & CPU_INTERRUPT_SMI) &&
@@ -405,9 +411,6 @@ int cpu_exec(CPUArchState *env) 
                        }

                    }

#elif defined(TARGET_PPC)

                    if ((interrupt_request & CPU_INTERRUPT_RESET)) {

                        cpu_reset(cpu);

                    }

                    if (interrupt_request & CPU_INTERRUPT_HARD) {

                        ppc_hw_interrupt(env);

                        if (env->pending_interrupts == 0) {

include/exec/cpu-all.h

+5 −3
Original line number Diff line number Diff line
@@ -381,6 +381,9 @@ CPUArchState *cpu_copy(CPUArchState *env); 
/* Debug event pending.  */

#define CPU_INTERRUPT_DEBUG       0x0080



/* Reset signal.  */

#define CPU_INTERRUPT_RESET       0x0400



/* Several target-specific external hardware interrupts.  Each target/cpu.h

   should define proper names based on these defines.  */

#define CPU_INTERRUPT_TGT_EXT_0   0x0008
@@ -395,9 +398,8 @@ CPUArchState *cpu_copy(CPUArchState *env); 
   instruction being executed.  These, therefore, are not masked while

   single-stepping within the debugger.  */

#define CPU_INTERRUPT_TGT_INT_0   0x0100

#define CPU_INTERRUPT_TGT_INT_1   0x0400

#define CPU_INTERRUPT_TGT_INT_2   0x0800

#define CPU_INTERRUPT_TGT_INT_3   0x2000

#define CPU_INTERRUPT_TGT_INT_1   0x0800

#define CPU_INTERRUPT_TGT_INT_2   0x2000



/* First unused bit: 0x4000.  */

target-i386/cpu.h

+4 −3
Original line number Diff line number Diff line
@@ -606,10 +606,11 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; 
#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3

#define CPU_INTERRUPT_MCE       CPU_INTERRUPT_TGT_EXT_4

#define CPU_INTERRUPT_VIRQ      CPU_INTERRUPT_TGT_INT_0

#define CPU_INTERRUPT_INIT      CPU_INTERRUPT_TGT_INT_1

#define CPU_INTERRUPT_SIPI      CPU_INTERRUPT_TGT_INT_2

#define CPU_INTERRUPT_TPR       CPU_INTERRUPT_TGT_INT_3

#define CPU_INTERRUPT_SIPI      CPU_INTERRUPT_TGT_INT_1

#define CPU_INTERRUPT_TPR       CPU_INTERRUPT_TGT_INT_2



/* Use a clearer name for this.  */

#define CPU_INTERRUPT_INIT      CPU_INTERRUPT_RESET



typedef enum {

    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */

target-ppc/cpu.h

+0 −3
Original line number Diff line number Diff line
@@ -2042,9 +2042,6 @@ enum { 
    PPC_INTERRUPT_PERFM,          /* Performance monitor interrupt        */

};



/* CPU should be reset next, restart from scratch afterwards */

#define CPU_INTERRUPT_RESET       CPU_INTERRUPT_TGT_INT_0



/*****************************************************************************/



static inline target_ulong cpu_read_xer(CPUPPCState *env)