Commit 46beb58e authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Convert T16, load (literal) 



Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-66-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 151c2f28

target/arm/t16.decode

+4 −0
Original line number Diff line number Diff line
@@ -113,6 +113,10 @@ LDRH_ri 10001 ..... ... ... @ldst_ri_2 
STR_ri          10010 ... ........              @ldst_spec_i rn=13

LDR_ri          10011 ... ........              @ldst_spec_i rn=13



# Load (PC-relative)



LDR_ri          01001 ... ........              @ldst_spec_i rn=15



# Add PC/SP (immediate)



ADR             10100 rd:3 ........             imm=%imm8_0x4

target/arm/translate.c

+2 −40
Original line number Diff line number Diff line
@@ -982,14 +982,6 @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ 
                                     TCGv_i32 a32, int index)            \

{                                                                        \

    gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data);               \

}                                                                        \

static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s,              \

                                           TCGv_i32 val,                 \

                                           TCGv_i32 a32, int index,      \

                                           ISSInfo issinfo)              \

{                                                                        \

    gen_aa32_ld##SUFF(s, val, a32, index);                               \

    disas_set_da_iss(s, OPC, issinfo);                                   \

}



#define DO_GEN_ST(SUFF, OPC)                                             \
@@ -997,14 +989,6 @@ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ 
                                     TCGv_i32 a32, int index)            \

{                                                                        \

    gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data);               \

}                                                                        \

static inline void gen_aa32_st##SUFF##_iss(DisasContext *s,              \

                                           TCGv_i32 val,                 \

                                           TCGv_i32 a32, int index,      \

                                           ISSInfo issinfo)              \

{                                                                        \

    gen_aa32_st##SUFF(s, val, a32, index);                               \

    disas_set_da_iss(s, OPC, issinfo | ISSIsWrite);                      \

}



static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
@@ -1053,9 +1037,7 @@ static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, 
    gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data);

}



DO_GEN_LD(8s, MO_SB)

DO_GEN_LD(8u, MO_UB)

DO_GEN_LD(16s, MO_SW)

DO_GEN_LD(16u, MO_UW)

DO_GEN_LD(32u, MO_UL)

DO_GEN_ST(8, MO_UB)
@@ -10754,11 +10736,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) 


static void disas_thumb_insn(DisasContext *s, uint32_t insn)

{

    uint32_t val, rd;

    uint32_t val;

    int32_t offset;

    TCGv_i32 tmp;

    TCGv_i32 tmp2;

    TCGv_i32 addr;



    if (disas_t16(s, insn)) {

        return;
@@ -10768,26 +10749,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) 
    switch (insn >> 12) {

    case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */

    case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */

        goto illegal_op;

    case 4:

        if (insn & (1 << 11)) {

            rd = (insn >> 8) & 7;

            /* load pc-relative.  Bit 1 of PC is ignored.  */

            addr = add_reg_for_lit(s, 15, (insn & 0xff) * 4);

            tmp = tcg_temp_new_i32();

            gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),

                               rd | ISSIs16Bit);

            tcg_temp_free_i32(addr);

            store_reg(s, rd, tmp);

            break;

        }



        /*

         * - Data-processing (two low registers), in decodetree

         * - data processing extended, branch and exchange, in decodetree

         */

        goto illegal_op;



    case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree */

    case 5: /* load/store register offset, in decodetree */

    case 6: /* load/store word immediate offset, in decodetree */

    case 7: /* load/store byte immediate offset, in decodetree */