Commit 151c2f28 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Convert T16, shift immediate 



Reviewed-by: default avatarPhilippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-65-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 43f7e42c

target/arm/t16.decode

+8 −0
Original line number Diff line number Diff line
@@ -126,6 +126,14 @@ ADD_rri 10101 rd:3 ........ \ 
STM             11000 ... ........              @ldstm

LDM_t16         11001 ... ........              @ldstm



# Shift (immediate)



@shift_i        ..... shim:5 rm:3 rd:3          &s_rrr_shi %s rn=%reg_0



MOV_rxri        000 00 ..... ... ...            @shift_i shty=0  # LSL

MOV_rxri        000 01 ..... ... ...            @shift_i shty=1  # LSR

MOV_rxri        000 10 ..... ... ...            @shift_i shty=2  # ASR



# Add/subtract (three low registers)



@addsub_3       ....... rm:3 rn:3 rd:3 \

target/arm/translate.c

+2 −24
Original line number Diff line number Diff line
@@ -10754,7 +10754,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) 


static void disas_thumb_insn(DisasContext *s, uint32_t insn)

{

    uint32_t val, op, rm, rd, shift;

    uint32_t val, rd;

    int32_t offset;

    TCGv_i32 tmp;

    TCGv_i32 tmp2;
@@ -10766,29 +10766,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) 
    /* fall back to legacy decoder */



    switch (insn >> 12) {

    case 0: case 1:



        rd = insn & 7;

        op = (insn >> 11) & 3;

        if (op == 3) {

            /*

             * 0b0001_1xxx_xxxx_xxxx

             *  - Add, subtract (three low registers)

             *  - Add, subtract (two low registers and immediate)

             * In decodetree.

             */

            goto illegal_op;

        } else {

            /* shift immediate */

            rm = (insn >> 3) & 7;

            shift = (insn >> 6) & 0x1f;

            tmp = load_reg(s, rm);

            gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0);

            if (!s->condexec_mask)

                gen_logic_CC(tmp);

            store_reg(s, rd, tmp);

        }

        break;

    case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */

    case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */

        goto illegal_op;

    case 4: