Commit 44829396 authored by Edgar E. Iglesias's avatar Edgar E. Iglesias
Browse files

Merge remote branch 'rth/axp-next' into alpha-merge 

* rth/axp-next: (26 commits)
  target-alpha: Implement TLB flush primitives.
  target-alpha: Use a fixed frequency for the RPCC in system mode.
  target-alpha: Trap for unassigned and unaligned addresses.
  target-alpha: Remap PIO space for 43-bit KSEG for EV6.
  target-alpha: Implement cpu_alpha_handle_mmu_fault for system mode.
  target-alpha: Implement more CALL_PAL values inline.
  target-alpha: Disable interrupts properly.
  target-alpha: All ISA checks to use TB->FLAGS.
  target-alpha: Swap shadow registers moving to/from PALmode.
  target-alpha: Implement do_interrupt for system mode.
  target-alpha: Add IPRs to be used by the emulation PALcode.
  target-alpha: Use kernel mmu_idx for pal_mode.
  target-alpha: Add various symbolic constants.
  target-alpha: Use do_restore_state for arithmetic exceptions.
  target-alpha: Tidy up arithmetic exceptions.
  target-alpha: Tidy exception constants.
  target-alpha: Enable the alpha-softmmu target.
  target-alpha: Rationalize internal processor registers.
  target-alpha: Merge HW_REI and HW_RET implementations.
  target-alpha: Cleanup MMU modes.
  ...
parents 1c532d92 3b4fefd6

MAINTAINERS

+2 −2
Original line number Diff line number Diff line
@@ -56,8 +56,8 @@ M: Paul Brook <paul@codesourcery.com> 
Guest CPU cores (TCG):

----------------------

Alpha

M: qemu-devel@nongnu.org

S: Orphan

M: Richard Henderson <rth@twiddle.net>

S: Maintained

F: target-alpha/



ARM

Makefile.target

+2 −1
Original line number Diff line number Diff line
@@ -374,7 +374,8 @@ obj-m68k-y += m68k-semi.o dummy_m68k.o 


obj-s390x-y = s390-virtio-bus.o s390-virtio.o



obj-alpha-y = alpha_palcode.o

obj-alpha-y = i8259.o mc146818rtc.o

obj-alpha-y += vga.o cirrus_vga.o



main.o: QEMU_CFLAGS+=$(GPROF_CFLAGS)

alpha-dis.c

+0 −4
Original line number Diff line number Diff line
@@ -238,10 +238,6 @@ extern const unsigned alpha_num_operands; 
#define AXP_REG_SP	30

#define AXP_REG_ZERO	31



#define bfd_mach_alpha_ev4  0x10

#define bfd_mach_alpha_ev5  0x20

#define bfd_mach_alpha_ev6  0x30



enum bfd_reloc_code_real {

    BFD_RELOC_23_PCREL_S2,

    BFD_RELOC_ALPHA_HINT

configure

+1 −0
Original line number Diff line number Diff line
@@ -831,6 +831,7 @@ if [ "$softmmu" = "yes" ] ; then 
    default_target_list="\

i386-softmmu \

x86_64-softmmu \

alpha-softmmu \

arm-softmmu \

cris-softmmu \

lm32-softmmu \

cpu-exec.c

+30 −3
Original line number Diff line number Diff line
@@ -488,10 +488,37 @@ int cpu_exec(CPUState *env1) 
                        next_tb = 0;

                    }

#elif defined(TARGET_ALPHA)

                    {

                        int idx = -1;

                        /* ??? This hard-codes the OSF/1 interrupt levels.  */

		        switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {

                        case 0 ... 3:

                            if (interrupt_request & CPU_INTERRUPT_HARD) {

                                idx = EXCP_DEV_INTERRUPT;

                            }

                            /* FALLTHRU */

                        case 4:

                            if (interrupt_request & CPU_INTERRUPT_TIMER) {

                                idx = EXCP_CLK_INTERRUPT;

                            }

                            /* FALLTHRU */

                        case 5:

                            if (interrupt_request & CPU_INTERRUPT_SMP) {

                                idx = EXCP_SMP_INTERRUPT;

                            }

                            /* FALLTHRU */

                        case 6:

                            if (interrupt_request & CPU_INTERRUPT_MCHK) {

                                idx = EXCP_MCHK;

                            }

                        }

                        if (idx >= 0) {

                            env->exception_index = idx;

                            env->error_code = 0;

                            do_interrupt(env);

                            next_tb = 0;

                        }

                    }

#elif defined(TARGET_CRIS)

                    if (interrupt_request & CPU_INTERRUPT_HARD

                        && (env->pregs[PR_CCS] & I_FLAG)