Commit 3b4fefd6 authored by Richard Henderson's avatar Richard Henderson Committed by Richard Henderson
Browse files

target-alpha: Implement TLB flush primitives. 



Expose these via MTPR, more or less like the real HW does.

Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent e5214853

target-alpha/helper.h

+3 −0
Original line number Diff line number Diff line
@@ -110,6 +110,9 @@ DEF_HELPER_2(stl_phys, void, i64, i64) 
DEF_HELPER_2(stq_phys, void, i64, i64)

DEF_HELPER_2(stl_c_phys, i64, i64, i64)

DEF_HELPER_2(stq_c_phys, i64, i64, i64)



DEF_HELPER_FLAGS_0(tbia, TCG_CALL_CONST, void)

DEF_HELPER_FLAGS_1(tbis, TCG_CALL_CONST, void, i64)

#endif



#include "def-helper.h"

target-alpha/op_helper.c

+10 −1
Original line number Diff line number Diff line
@@ -1205,6 +1205,16 @@ void helper_hw_ret (uint64_t a) 
        swap_shadow_regs(env);

    }

}



void helper_tbia(void)

{

    tlb_flush(env, 1);

}



void helper_tbis(uint64_t p)

{

    tlb_flush_page(env, p);

}

#endif



/*****************************************************************************/
@@ -1335,5 +1345,4 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr) 
    }

    env = saved_env;

}



#endif

target-alpha/translate.c

+21 −11
Original line number Diff line number Diff line
@@ -1621,7 +1621,6 @@ static void gen_mfpr(int ra, int regno) 
static void gen_mtpr(int rb, int regno)

{

    TCGv tmp;

    int data;



    if (rb == 31) {

        tmp = tcg_const_i64(0);
@@ -1629,9 +1628,19 @@ static void gen_mtpr(int rb, int regno) 
        tmp = cpu_ir[rb];

    }



    /* These two register numbers perform a TLB cache flush.  Thankfully we

       can only do this inside PALmode, which means that the current basic

       block cannot be affected by the change in mappings.  */

    if (regno == 255) {

        /* TBIA */

        gen_helper_tbia();

    } else if (regno == 254) {

        /* TBIS */

        gen_helper_tbis(tmp);

    } else {

        /* The basic registers are data only, and unknown registers

           are read-zero, write-ignore.  */

    data = cpu_pr_data(regno);

        int data = cpu_pr_data(regno);

        if (data != 0) {

            if (data & PR_BYTE) {

                tcg_gen_st8_i64(tmp, cpu_env, data & ~PR_BYTE);
@@ -1641,6 +1650,7 @@ static void gen_mtpr(int rb, int regno) 
                tcg_gen_st_i64(tmp, cpu_env, data);

            }

        }

    }



    if (rb == 31) {

        tcg_temp_free(tmp);