Commit 3fa18bc9 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/xtensa/tags/20150706-xtensa' into staging 



Xtensa fixes:

- add 64-bit floating point registers;
- fix gdb register map construction.

# gpg: Signature made Mon Jul  6 11:27:45 2015 BST using RSA key ID F83FA044
# gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>"
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>"

* remotes/xtensa/tags/20150706-xtensa:
  target-xtensa: fix gdb register map construction
  target-xtensa: add 64-bit floating point registers

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 261ccf42 1479073b

target-xtensa/core-dc232b.c

+1 −1
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ 
#include "core-dc232b/core-isa.h"

#include "overlay_tool.h"



static const XtensaConfig dc232b __attribute__((unused)) = {

static XtensaConfig dc232b __attribute__((unused)) = {

    .name = "dc232b",

    .gdb_regmap = {

        .num_regs = 120,

target-xtensa/core-dc233c.c

+1 −1
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ 
#include "core-dc233c/core-isa.h"

#include "overlay_tool.h"



static const XtensaConfig dc233c __attribute__((unused)) = {

static XtensaConfig dc233c __attribute__((unused)) = {

    .name = "dc233c",

    .gdb_regmap = {

        .num_regs = 121,

target-xtensa/core-fsf.c

+6 −1
Original line number Diff line number Diff line
@@ -33,9 +33,14 @@ 
#include "core-fsf/core-isa.h"

#include "overlay_tool.h"



static const XtensaConfig fsf __attribute__((unused)) = {

static XtensaConfig fsf __attribute__((unused)) = {

    .name = "fsf",

    .gdb_regmap = {

    /* GDB for this core is not supported currently */

        .reg = {

            XTREG_END

        },

    },

    .clock_freq_khz = 10000,

    DEFAULT_SECTIONS

};

target-xtensa/cpu.h

+18 −1
Original line number Diff line number Diff line
@@ -287,6 +287,7 @@ typedef struct XtensaGdbReg { 
    int targno;

    int type;

    int group;

    unsigned size;

} XtensaGdbReg;



typedef struct XtensaGdbRegmap {
@@ -336,6 +337,18 @@ typedef struct XtensaConfigList { 
    struct XtensaConfigList *next;

} XtensaConfigList;



#ifdef HOST_WORDS_BIGENDIAN

enum {

    FP_F32_HIGH,

    FP_F32_LOW,

};

#else

enum {

    FP_F32_LOW,

    FP_F32_HIGH,

};

#endif



typedef struct CPUXtensaState {

    const XtensaConfig *config;

    uint32_t regs[16];
@@ -343,7 +356,10 @@ typedef struct CPUXtensaState { 
    uint32_t sregs[256];

    uint32_t uregs[256];

    uint32_t phys_regs[MAX_NAREG];

    float32 fregs[16];

    union {

        float32 f32[2];

        float64 f64;

    } fregs[16];

    float_status fp_status;



    xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
@@ -384,6 +400,7 @@ XtensaCPU *cpu_xtensa_init(const char *cpu_model); 
void xtensa_translate_init(void);

void xtensa_breakpoint_handler(CPUState *cs);

int cpu_xtensa_exec(CPUXtensaState *s);

void xtensa_finalize_config(XtensaConfig *config);

void xtensa_register_core(XtensaConfigList *node);

void check_interrupts(CPUXtensaState *s);

void xtensa_irq_init(CPUXtensaState *env);

target-xtensa/gdbstub.c

+21 −4
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) 
    XtensaCPU *cpu = XTENSA_CPU(cs);

    CPUXtensaState *env = &cpu->env;

    const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;

    unsigned i;



    if (n < 0 || n >= env->config->gdb_regmap.num_regs) {

        return 0;
@@ -47,8 +48,16 @@ int xtensa_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) 
        return gdb_get_reg32(mem_buf, env->uregs[reg->targno & 0xff]);



    case 4: /*f*/

        return gdb_get_reg32(mem_buf, float32_val(env->fregs[reg->targno

                                                             & 0x0f]));

        i = reg->targno & 0x0f;

        switch (reg->size) {

        case 4:

            return gdb_get_reg32(mem_buf,

                                 float32_val(env->fregs[i].f32[FP_F32_LOW]));

        case 8:

            return gdb_get_reg64(mem_buf, float64_val(env->fregs[i].f64));

        default:

            return 0;

        }



    case 8: /*a*/

        return gdb_get_reg32(mem_buf, env->regs[reg->targno & 0x0f]);
@@ -92,8 +101,16 @@ int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) 
        break;



    case 4: /*f*/

        env->fregs[reg->targno & 0x0f] = make_float32(tmp);

        break;

        switch (reg->size) {

        case 4:

            env->fregs[reg->targno & 0x0f].f32[FP_F32_LOW] = make_float32(tmp);

            return 4;

        case 8:

            env->fregs[reg->targno & 0x0f].f64 = make_float64(tmp);

            return 8;

        default:

            return 0;

        }



    case 8: /*a*/

        env->regs[reg->targno & 0x0f] = tmp;