Commit 3b886706 authored by Blue Swirl's avatar Blue Swirl
Browse files

Merge branch 'ppc-next' of git://repo.or.cz/qemu/agraf 

* 'ppc-next' of git://repo.or.cz/qemu/agraf:
  PPC: move TLBs to their own arrays
  PPC: 440: Use 440 style MMU as default, so Qemu knows the MMU type
  PPC: E500: Use MAS registers instead of internal TLB representation
  PPC: Only set lower 32bits with mtmsr
  PPC: update openbios firmware
  PPC: mpc8544ds: Add hypervisor node
  PPC: calculate kernel,initrd,cmdline locations dynamically
  target-ppc: Handle memory-forced I/O controller access
  PPC: E500: Implement reboot controller
parents ec188429 1c53accc

Makefile.target

+1 −1
Original line number Diff line number Diff line
@@ -260,7 +260,7 @@ endif 
obj-ppc-y += ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o

obj-ppc-y += ppc440.o ppc440_bamboo.o

# PowerPC E500 boards

obj-ppc-y += ppce500_mpc8544ds.o

obj-ppc-y += ppce500_mpc8544ds.o mpc8544_guts.o

# PowerPC 440 Xilinx ML507 reference board.

obj-ppc-y += virtex_ml507.o

obj-ppc-$(CONFIG_KVM) += kvm_ppc.o

hw/mpc8544_guts.c

0 → 100644
+135 −0
Original line number Diff line number Diff line 
/*

 * QEMU PowerPC MPC8544 global util pseudo-device

 *

 * Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved.

 *

 * Author: Alexander Graf, <alex@csgraf.de>

 *

 * This is free software; you can redistribute it and/or modify

 * it under the terms of  the GNU General  Public License as published by

 * the Free Software Foundation;  either version 2 of the  License, or

 * (at your option) any later version.

 *

 * *****************************************************************

 *

 * The documentation for this device is noted in the MPC8544 documentation,

 * file name "MPC8544ERM.pdf". You can easily find it on the web.

 *

 */



#include "hw.h"

#include "sysemu.h"

#include "sysbus.h"



#define MPC8544_GUTS_MMIO_SIZE        0x1000

#define MPC8544_GUTS_RSTCR_RESET      0x02



#define MPC8544_GUTS_ADDR_PORPLLSR    0x00

#define MPC8544_GUTS_ADDR_PORBMSR     0x04

#define MPC8544_GUTS_ADDR_PORIMPSCR   0x08

#define MPC8544_GUTS_ADDR_PORDEVSR    0x0C

#define MPC8544_GUTS_ADDR_PORDBGMSR   0x10

#define MPC8544_GUTS_ADDR_PORDEVSR2   0x14

#define MPC8544_GUTS_ADDR_GPPORCR     0x20

#define MPC8544_GUTS_ADDR_GPIOCR      0x30

#define MPC8544_GUTS_ADDR_GPOUTDR     0x40

#define MPC8544_GUTS_ADDR_GPINDR      0x50

#define MPC8544_GUTS_ADDR_PMUXCR      0x60

#define MPC8544_GUTS_ADDR_DEVDISR     0x70

#define MPC8544_GUTS_ADDR_POWMGTCSR   0x80

#define MPC8544_GUTS_ADDR_MCPSUMR     0x90

#define MPC8544_GUTS_ADDR_RSTRSCR     0x94

#define MPC8544_GUTS_ADDR_PVR         0xA0

#define MPC8544_GUTS_ADDR_SVR         0xA4

#define MPC8544_GUTS_ADDR_RSTCR       0xB0

#define MPC8544_GUTS_ADDR_IOVSELSR    0xC0

#define MPC8544_GUTS_ADDR_DDRCSR      0xB20

#define MPC8544_GUTS_ADDR_DDRCDR      0xB24

#define MPC8544_GUTS_ADDR_DDRCLKDR    0xB28

#define MPC8544_GUTS_ADDR_CLKOCR      0xE00

#define MPC8544_GUTS_ADDR_SRDS1CR1    0xF04

#define MPC8544_GUTS_ADDR_SRDS2CR1    0xF10

#define MPC8544_GUTS_ADDR_SRDS2CR3    0xF18



struct GutsState {

    SysBusDevice busdev;

};



typedef struct GutsState GutsState;



static uint32_t mpc8544_guts_read32(void *opaque, target_phys_addr_t addr)

{

    uint32_t value = 0;

    CPUState *env = cpu_single_env;



    addr &= MPC8544_GUTS_MMIO_SIZE - 1;

    switch (addr) {

    case MPC8544_GUTS_ADDR_PVR:

        value = env->spr[SPR_PVR];

        break;

    case MPC8544_GUTS_ADDR_SVR:

        value = env->spr[SPR_E500_SVR];

        break;

    default:

        fprintf(stderr, "guts: Unknown register read: %x\n", (int)addr);

        break;

    }



    return value;

}



static CPUReadMemoryFunc * const mpc8544_guts_read[] = {

    NULL,

    NULL,

    &mpc8544_guts_read32,

};



static void mpc8544_guts_write32(void *opaque, target_phys_addr_t addr,

                              uint32_t value)

{

    addr &= MPC8544_GUTS_MMIO_SIZE - 1;



    switch (addr) {

    case MPC8544_GUTS_ADDR_RSTCR:

        if (value & MPC8544_GUTS_RSTCR_RESET) {

            qemu_system_reset_request();

        }

        break;

    default:

        fprintf(stderr, "guts: Unknown register write: %x = %x\n",

                (int)addr, value);

        break;

    }

}



static CPUWriteMemoryFunc * const mpc8544_guts_write[] = {

    NULL,

    NULL,

    &mpc8544_guts_write32,

};



static int mpc8544_guts_initfn(SysBusDevice *dev)

{

    GutsState *s;

    int iomem;



    s = FROM_SYSBUS(GutsState, sysbus_from_qdev(dev));



    iomem = cpu_register_io_memory(mpc8544_guts_read, mpc8544_guts_write, s,

                                   DEVICE_BIG_ENDIAN);

    sysbus_init_mmio(dev, MPC8544_GUTS_MMIO_SIZE, iomem);



    return 0;

}



static SysBusDeviceInfo mpc8544_guts_info = {

    .init         = mpc8544_guts_initfn,

    .qdev.name    = "mpc8544-guts",

    .qdev.size    = sizeof(GutsState),

};



static void mpc8544_guts_register(void)

{

    sysbus_register_withprop(&mpc8544_guts_info);

}

device_init(mpc8544_guts_register);

hw/ppc440.c

+3 −2
Original line number Diff line number Diff line
@@ -45,8 +45,9 @@ CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip, 
    qemu_irq *irqs;

    qemu_irq *pci_irqs;



    if (cpu_model == NULL)

        cpu_model = "405"; // XXX: should be 440EP

    if (cpu_model == NULL) {

        cpu_model = "440-Xilinx"; // XXX: should be 440EP

    }

    env = cpu_init(cpu_model);

    if (!env) {

        fprintf(stderr, "Unable to initialize CPU!\n");

hw/ppc_mac.h

+1 −2
Original line number Diff line number Diff line
@@ -35,8 +35,7 @@ 
#define PROM_ADDR         0xfff00000



#define KERNEL_LOAD_ADDR 0x01000000

#define CMDLINE_ADDR     0x027ff000

#define INITRD_LOAD_ADDR 0x02800000

#define KERNEL_GAP       0x00100000



#define ESCC_CLOCK 3686400

hw/ppc_newworld.c

+11 −4
Original line number Diff line number Diff line
@@ -120,6 +120,11 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 
    return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;

}



static target_phys_addr_t round_page(target_phys_addr_t addr)

{

    return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;

}



/* PowerPC Mac99 hardware initialisation */

static void ppc_core99_init (ram_addr_t ram_size,

                             const char *boot_device,
@@ -134,7 +139,7 @@ static void ppc_core99_init (ram_addr_t ram_size, 
    int unin_memory;

    int linux_boot, i;

    ram_addr_t ram_offset, bios_offset;

    uint32_t kernel_base, initrd_base;

    target_phys_addr_t kernel_base, initrd_base, cmdline_base = 0;

    long kernel_size, initrd_size;

    PCIBus *pci_bus;

    MacIONVRAMState *nvr;
@@ -220,7 +225,7 @@ static void ppc_core99_init (ram_addr_t ram_size, 
        }

        /* load initrd */

        if (initrd_filename) {

            initrd_base = INITRD_LOAD_ADDR;

            initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);

            initrd_size = load_image_targphys(initrd_filename, initrd_base,

                                              ram_size - initrd_base);

            if (initrd_size < 0) {
@@ -228,9 +233,11 @@ static void ppc_core99_init (ram_addr_t ram_size, 
                         initrd_filename);

                exit(1);

            }

            cmdline_base = round_page(initrd_base + initrd_size);

        } else {

            initrd_base = 0;

            initrd_size = 0;

            cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);

        }

        ppc_boot_device = 'm';

    } else {
@@ -373,8 +380,8 @@ static void ppc_core99_init (ram_addr_t ram_size, 
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);

    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);

    if (kernel_cmdline) {

        fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);

        pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);

        fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);

        pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);

    } else {

        fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);

    }