Commit 1c53accc authored by Alexander Graf's avatar Alexander Graf
Browse files

PPC: move TLBs to their own arrays 



Until now, we've created a union over multiple different TLB types and
allocated that union. While it's a waste of memory (and cache) to allocate
TLB information for a TLB type with much information when you only need
little, it also inflicts another issue.

With the new KVM API, we can now share the TLB between KVM and qemu, but
for that to work we need to have both be in the same layout. We can't just
stretch it over to fit some internal different TLB representation.

Hence this patch moves all TLB types to their own array, allowing us to only
address and allocate exactly the boundaries required for the specific TLB
type at hand.

Signed-off-by: default avatarAlexander Graf <agraf@suse.de>
parent 0dd4bc7d

hw/virtex_ml507.c

+2 −2
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ static void mmubooke_create_initial_mapping(CPUState *env, 
                                     target_ulong va,

                                     target_phys_addr_t pa)

{

    ppcemb_tlb_t *tlb = &env->tlb[0].tlbe;

    ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];



    tlb->attr = 0;

    tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
@@ -69,7 +69,7 @@ static void mmubooke_create_initial_mapping(CPUState *env, 
    tlb->RPN = pa & TARGET_PAGE_MASK;

    tlb->PID = 0;



    tlb = &env->tlb[1].tlbe;

    tlb = &env->tlb.tlbe[1];

    tlb->attr = 0;

    tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);

    tlb->size = 1 << 31; /* up to 0xffffffff  */

target-ppc/cpu.h

+14 −7
Original line number Diff line number Diff line
@@ -368,10 +368,16 @@ typedef struct ppcmas_tlb_t { 
} ppcmas_tlb_t;



union ppc_tlb_t {

    ppc6xx_tlb_t tlb6;

    ppcemb_tlb_t tlbe;

    ppcmas_tlb_t tlbm;

    ppc6xx_tlb_t *tlb6;

    ppcemb_tlb_t *tlbe;

    ppcmas_tlb_t *tlbm;

};



/* possible TLB variants */

#define TLB_NONE               0

#define TLB_6XX                1

#define TLB_EMB                2

#define TLB_MAS                3

#endif



#define SDR_32_HTABORG         0xFFFF0000UL
@@ -911,7 +917,8 @@ struct CPUPPCState { 
    int last_way;    /* Last used way used to allocate TLB in a LRU way      */

    int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */

    int nb_pids;     /* Number of available PID registers                    */

    ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */

    int tlb_type;    /* Type of TLB we're dealing with                       */

    ppc_tlb_t tlb;   /* TLB is optional. Allocate them only if needed        */

    /* 403 dedicated access protection registers */

    target_ulong pb[4];

#endif
@@ -1942,9 +1949,9 @@ static inline void cpu_set_tls(CPUState *env, target_ulong newtls) 
static inline int booke206_tlbm_id(CPUState *env, ppcmas_tlb_t *tlbm)

{

    uintptr_t tlbml = (uintptr_t)tlbm;

    uintptr_t tlbl = (uintptr_t)env->tlb;

    uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;



    return (tlbml - tlbl) / sizeof(env->tlb[0]);

    return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);

}



static inline int booke206_tlb_size(CPUState *env, int tlbn)
@@ -2004,7 +2011,7 @@ static inline ppcmas_tlb_t *booke206_get_tlbm(CPUState *env, const int tlbn, 
        r += booke206_tlb_size(env, i);

    }



    return &env->tlb[r].tlbm;

    return &env->tlb.tlbm[r];

}



#endif

target-ppc/helper.c

+13 −13
Original line number Diff line number Diff line
@@ -323,7 +323,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUState *env) 
    if (env->id_tlbs == 1)

        max *= 2;

    for (nr = 0; nr < max; nr++) {

        tlb = &env->tlb[nr].tlb6;

        tlb = &env->tlb.tlb6[nr];

        pte_invalidate(&tlb->pte0);

    }

    tlb_flush(env, 1);
@@ -340,7 +340,7 @@ static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env, 
    /* Invalidate ITLB + DTLB, all ways */

    for (way = 0; way < env->nb_ways; way++) {

        nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);

        tlb = &env->tlb[nr].tlb6;

        tlb = &env->tlb.tlb6[nr];

        if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {

            LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr,

                      env->nb_tlb, eaddr);
@@ -367,7 +367,7 @@ void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code, 
    int nr;



    nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);

    tlb = &env->tlb[nr].tlb6;

    tlb = &env->tlb.tlb6[nr];

    LOG_SWTLB("Set TLB %d/%d EPN " TARGET_FMT_lx " PTE0 " TARGET_FMT_lx

              " PTE1 " TARGET_FMT_lx "\n", nr, env->nb_tlb, EPN, pte0, pte1);

    /* Invalidate any pending reference in Qemu for this virtual address */
@@ -391,7 +391,7 @@ static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx, 
    for (way = 0; way < env->nb_ways; way++) {

        nr = ppc6xx_tlb_getnum(env, eaddr, way,

                               access_type == ACCESS_CODE ? 1 : 0);

        tlb = &env->tlb[nr].tlb6;

        tlb = &env->tlb.tlb6[nr];

        /* This test "emulates" the PTE index match for hardware TLBs */

        if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {

            LOG_SWTLB("TLB %d/%d %s [" TARGET_FMT_lx " " TARGET_FMT_lx
@@ -434,7 +434,7 @@ static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx, 
        LOG_SWTLB("found TLB at addr " TARGET_FMT_plx " prot=%01x ret=%d\n",

                  ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);

        /* Update page flags */

        pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);

        pte_update_flags(ctx, &env->tlb.tlb6[best].pte1, ret, rw);

    }



    return ret;
@@ -1049,7 +1049,7 @@ int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid) 
    /* Default return value is no match */

    ret = -1;

    for (i = 0; i < env->nb_tlb; i++) {

        tlb = &env->tlb[i].tlbe;

        tlb = &env->tlb.tlbe[i];

        if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {

            ret = i;

            break;
@@ -1066,7 +1066,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUState *env) 
    int i;



    for (i = 0; i < env->nb_tlb; i++) {

        tlb = &env->tlb[i].tlbe;

        tlb = &env->tlb.tlbe[i];

        tlb->prot &= ~PAGE_VALID;

    }

    tlb_flush(env, 1);
@@ -1082,7 +1082,7 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUState *env, 
    int i;



    for (i = 0; i < env->nb_tlb; i++) {

        tlb = &env->tlb[i].tlbe;

        tlb = &env->tlb.tlbe[i];

        if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {

            end = tlb->EPN + tlb->size;

            for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
@@ -1107,7 +1107,7 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx, 
    raddr = (target_phys_addr_t)-1ULL;

    pr = msr_pr;

    for (i = 0; i < env->nb_tlb; i++) {

        tlb = &env->tlb[i].tlbe;

        tlb = &env->tlb.tlbe[i];

        if (ppcemb_tlb_check(env, tlb, &raddr, address,

                             env->spr[SPR_40x_PID], 0, i) < 0)

            continue;
@@ -1248,7 +1248,7 @@ static int mmubooke_get_physical_address (CPUState *env, mmu_ctx_t *ctx, 
    ret = -1;

    raddr = (target_phys_addr_t)-1ULL;

    for (i = 0; i < env->nb_tlb; i++) {

        tlb = &env->tlb[i].tlbe;

        tlb = &env->tlb.tlbe[i];

        ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address, rw,

                                 access_type, i);

        if (!ret) {
@@ -1273,14 +1273,14 @@ void booke206_flush_tlb(CPUState *env, int flags, const int check_iprot) 
{

    int tlb_size;

    int i, j;

    ppc_tlb_t *tlb = env->tlb;

    ppcmas_tlb_t *tlb = env->tlb.tlbm;



    for (i = 0; i < BOOKE206_MAX_TLBN; i++) {

        if (flags & (1 << i)) {

            tlb_size = booke206_tlb_size(env, i);

            for (j = 0; j < tlb_size; j++) {

                if (!check_iprot || !(tlb[j].tlbm.mas1 & MAS1_IPROT)) {

                    tlb[j].tlbm.mas1 &= ~MAS1_VALID;

                if (!check_iprot || !(tlb[j].mas1 & MAS1_IPROT)) {

                    tlb[j].mas1 &= ~MAS1_VALID;

                }

            }

        }

target-ppc/machine.c

+8 −8
Original line number Diff line number Diff line
@@ -52,12 +52,12 @@ void cpu_save(QEMUFile *f, void *opaque) 
    qemu_put_sbe32s(f, &env->last_way);

    qemu_put_sbe32s(f, &env->id_tlbs);

    qemu_put_sbe32s(f, &env->nb_pids);

    if (env->tlb) {

    if (env->tlb.tlb6) {

        // XXX assumes 6xx

        for (i = 0; i < env->nb_tlb; i++) {

            qemu_put_betls(f, &env->tlb[i].tlb6.pte0);

            qemu_put_betls(f, &env->tlb[i].tlb6.pte1);

            qemu_put_betls(f, &env->tlb[i].tlb6.EPN);

            qemu_put_betls(f, &env->tlb.tlb6[i].pte0);

            qemu_put_betls(f, &env->tlb.tlb6[i].pte1);

            qemu_put_betls(f, &env->tlb.tlb6[i].EPN);

        }

    }

    for (i = 0; i < 4; i++)
@@ -140,12 +140,12 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) 
    qemu_get_sbe32s(f, &env->last_way);

    qemu_get_sbe32s(f, &env->id_tlbs);

    qemu_get_sbe32s(f, &env->nb_pids);

    if (env->tlb) {

    if (env->tlb.tlb6) {

        // XXX assumes 6xx

        for (i = 0; i < env->nb_tlb; i++) {

            qemu_get_betls(f, &env->tlb[i].tlb6.pte0);

            qemu_get_betls(f, &env->tlb[i].tlb6.pte1);

            qemu_get_betls(f, &env->tlb[i].tlb6.EPN);

            qemu_get_betls(f, &env->tlb.tlb6[i].pte0);

            qemu_get_betls(f, &env->tlb.tlb6[i].pte1);

            qemu_get_betls(f, &env->tlb.tlb6[i].EPN);

        }

    }

    for (i = 0; i < 4; i++)

target-ppc/op_helper.c

+6 −6
Original line number Diff line number Diff line
@@ -3959,7 +3959,7 @@ target_ulong helper_4xx_tlbre_hi (target_ulong entry) 
    int size;



    entry &= PPC4XX_TLB_ENTRY_MASK;

    tlb = &env->tlb[entry].tlbe;

    tlb = &env->tlb.tlbe[entry];

    ret = tlb->EPN;

    if (tlb->prot & PAGE_VALID) {

        ret |= PPC4XX_TLBHI_V;
@@ -3979,7 +3979,7 @@ target_ulong helper_4xx_tlbre_lo (target_ulong entry) 
    target_ulong ret;



    entry &= PPC4XX_TLB_ENTRY_MASK;

    tlb = &env->tlb[entry].tlbe;

    tlb = &env->tlb.tlbe[entry];

    ret = tlb->RPN;

    if (tlb->prot & PAGE_EXEC) {

        ret |= PPC4XX_TLBLO_EX;
@@ -3998,7 +3998,7 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val) 
    LOG_SWTLB("%s entry %d val " TARGET_FMT_lx "\n", __func__, (int)entry,

              val);

    entry &= PPC4XX_TLB_ENTRY_MASK;

    tlb = &env->tlb[entry].tlbe;

    tlb = &env->tlb.tlbe[entry];

    /* Invalidate previous TLB (if it's valid) */

    if (tlb->prot & PAGE_VALID) {

        end = tlb->EPN + tlb->size;
@@ -4056,7 +4056,7 @@ void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val) 
    LOG_SWTLB("%s entry %i val " TARGET_FMT_lx "\n", __func__, (int)entry,

              val);

    entry &= PPC4XX_TLB_ENTRY_MASK;

    tlb = &env->tlb[entry].tlbe;

    tlb = &env->tlb.tlbe[entry];

    tlb->attr = val & PPC4XX_TLBLO_ATTR_MASK;

    tlb->RPN = val & PPC4XX_TLBLO_RPN_MASK;

    tlb->prot = PAGE_READ;
@@ -4091,7 +4091,7 @@ void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value) 
              __func__, word, (int)entry, value);

    do_flush_tlbs = 0;

    entry &= 0x3F;

    tlb = &env->tlb[entry].tlbe;

    tlb = &env->tlb.tlbe[entry];

    switch (word) {

    default:

        /* Just here to please gcc */
@@ -4150,7 +4150,7 @@ target_ulong helper_440_tlbre (uint32_t word, target_ulong entry) 
    int size;



    entry &= 0x3F;

    tlb = &env->tlb[entry].tlbe;

    tlb = &env->tlb.tlbe[entry];

    switch (word) {

    default:

        /* Just here to please gcc */