Commit 3a00d560 authored by Michael Davidsaver's avatar Michael Davidsaver Committed by Peter Maydell
Browse files

armv7m: Implement M profile default memory map 



Add support for the M profile default memory map which is used
if the MPU is not present or disabled.

The main differences in behaviour from implementing this
correctly are that we set the PAGE_EXEC attribute on
the right regions of memory, such that device regions
are not executable.

Signed-off-by: default avatarMichael Davidsaver <mdavidsaver@gmail.com>
Message-id: 1493122030-32191-10-git-send-email-peter.maydell@linaro.org
[PMM: rephrased comment and commit message; don't mark
 the flash memory region as not-writable; list all
 the cases in the default map explicitly rather than
 using a 'default' case for the non-executable regions]
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent c9f9f124

target/arm/helper.c

+32 −9
Original line number Diff line number Diff line
@@ -8129,10 +8129,12 @@ static inline void get_phys_addr_pmsav7_default(CPUARMState *env, 
                                                ARMMMUIdx mmu_idx,

                                                int32_t address, int *prot)

{

    if (!arm_feature(env, ARM_FEATURE_M)) {

        *prot = PAGE_READ | PAGE_WRITE;

        switch (address) {

        case 0xF0000000 ... 0xFFFFFFFF:

        if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */

            if (regime_sctlr(env, mmu_idx) & SCTLR_V) {

                /* hivecs execing is ok */

                *prot |= PAGE_EXEC;

            }

            break;
@@ -8140,7 +8142,28 @@ static inline void get_phys_addr_pmsav7_default(CPUARMState *env, 
            *prot |= PAGE_EXEC;

            break;

        }



    } else {

        /* Default system address map for M profile cores.

         * The architecture specifies which regions are execute-never;

         * at the MPU level no other checks are defined.

         */

        switch (address) {

        case 0x00000000 ... 0x1fffffff: /* ROM */

        case 0x20000000 ... 0x3fffffff: /* SRAM */

        case 0x60000000 ... 0x7fffffff: /* RAM */

        case 0x80000000 ... 0x9fffffff: /* RAM */

            *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;

            break;

        case 0x40000000 ... 0x5fffffff: /* Peripheral */

        case 0xa0000000 ... 0xbfffffff: /* Device */

        case 0xc0000000 ... 0xdfffffff: /* Device */

        case 0xe0000000 ... 0xffffffff: /* System */

            *prot = PAGE_READ | PAGE_WRITE;

            break;

        default:

            g_assert_not_reached();

        }

    }

}



static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,