Commit c9f9f124 authored by Michael Davidsaver's avatar Michael Davidsaver Committed by Peter Maydell
Browse files

armv7m: Improve "-d mmu" tracing for PMSAv7 MPU 



Improve the "-d mmu" tracing for the PMSAv7 MPU translation
process as an aid in debugging guest MPU configurations:
 * fix a missing newline for a guest-error log
 * report the region number with guest-error or unimp
   logs of bad region register values
 * add a log message for the overall result of the lookup
 * print "0x" prefix for hex values

Signed-off-by: default avatarMichael Davidsaver <mdavidsaver@gmail.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@xilinx.com>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1493122030-32191-9-git-send-email-peter.maydell@linaro.org
[PMM: a little tidyup, report region number in all messages
 rather than just one]
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent e9235c69

target/arm/helper.c

+27 −12
Original line number Diff line number Diff line
@@ -8169,16 +8169,18 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, 
            }



            if (!rsize) {

                qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");

                qemu_log_mask(LOG_GUEST_ERROR,

                              "DRSR[%d]: Rsize field cannot be 0\n", n);

                continue;

            }

            rsize++;

            rmask = (1ull << rsize) - 1;



            if (base & rmask) {

                qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "

                              "to DRSR region size, mask = %" PRIx32,

                              base, rmask);

                qemu_log_mask(LOG_GUEST_ERROR,

                              "DRBAR[%d]: 0x%" PRIx32 " misaligned "

                              "to DRSR region size, mask = 0x%" PRIx32 "\n",

                              n, base, rmask);

                continue;

            }
@@ -8215,9 +8217,10 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, 
                }

            }

            if (rsize < TARGET_PAGE_BITS) {

                qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"

                qemu_log_mask(LOG_UNIMP,

                              "DRSR[%d]: No support for MPU (sub)region "

                              "alignment of %" PRIu32 " bits. Minimum is %d\n",

                              rsize, TARGET_PAGE_BITS);

                              n, rsize, TARGET_PAGE_BITS);

                continue;

            }

            if (srdis) {
@@ -8251,8 +8254,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, 
                    break;

                default:

                    qemu_log_mask(LOG_GUEST_ERROR,

                                  "Bad value for AP bits in DRACR %"

                                  PRIx32 "\n", ap);

                                  "DRACR[%d]: Bad value for AP bits: 0x%"

                                  PRIx32 "\n", n, ap);

                }

            } else { /* Priv. mode AP bits decoding */

                switch (ap) {
@@ -8269,8 +8272,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, 
                    break;

                default:

                    qemu_log_mask(LOG_GUEST_ERROR,

                                  "Bad value for AP bits in DRACR %"

                                  PRIx32 "\n", ap);

                                  "DRACR[%d]: Bad value for AP bits: 0x%"

                                  PRIx32 "\n", n, ap);

                }

            }
@@ -8448,9 +8451,21 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address, 
     */

    if (arm_feature(env, ARM_FEATURE_PMSA) &&

        arm_feature(env, ARM_FEATURE_V7)) {

        bool ret;

        *page_size = TARGET_PAGE_SIZE;

        return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,

        ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx,

                                   phys_ptr, prot, fsr);

        qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRIx32

                      " mmu_idx %u -> %s (prot %c%c%c)\n",

                      access_type == 1 ? "reading" :

                      (access_type == 2 ? "writing" : "execute"),

                      (uint32_t)address, mmu_idx,

                      ret ? "Miss" : "Hit",

                      *prot & PAGE_READ ? 'r' : '-',

                      *prot & PAGE_WRITE ? 'w' : '-',

                      *prot & PAGE_EXEC ? 'x' : '-');



        return ret;

    }



    if (regime_translation_disabled(env, mmu_idx)) {