target/arm: Convert VQSHLU, VQSHL 2-reg-shift insns to decodetree (37bfce81) · Commits · SUMMER2020 / students / proj-2021291

target/arm/neon-dp.decode

+15 −0

Original line number	Diff line number	Diff line
		@@ -286,3 +286,18 @@ VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_d
		VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_s
		VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_h
		VSLI_2sh 1111 001 1 1 . ...... .... 0101 . . . 1 .... @2reg_shl_b

		VQSHLU_64_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_d
		VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_s
		VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_h
		VQSHLU_2sh 1111 001 1 1 . ...... .... 0110 . . . 1 .... @2reg_shl_b

		VQSHL_S_64_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
		VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
		VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
		VQSHL_S_2sh 1111 001 0 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b

		VQSHL_U_64_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_d
		VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_s
		VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_h
		VQSHL_U_2sh 1111 001 1 1 . ...... .... 0111 . . . 1 .... @2reg_shl_b

target/arm/translate-neon.inc.c

+108 −0

Original line number	Diff line number	Diff line
		@@ -1288,3 +1288,111 @@ static bool trans_VSHR_U_2sh(DisasContext s, arg_2reg_shift a)
		return do_vector_2sh(s, a, tcg_gen_gvec_shri);
		}
		}

		static bool do_2shift_env_64(DisasContext s, arg_2reg_shift a,
		NeonGenTwo64OpEnvFn *fn)
		{
		/*
		* 2-reg-and-shift operations, size == 3 case, where the
		* function needs to be passed cpu_env.
		*/
		TCGv_i64 constimm;
		int pass;

		if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
		return false;
		}

		/* UNDEF accesses to D16-D31 if they don't exist. */
		if (!dc_isar_feature(aa32_simd_r32, s) &&
		((a->vd \| a->vm) & 0x10)) {
		return false;
		}

		if ((a->vm \| a->vd) & a->q) {
		return false;
		}

		if (!vfp_access_check(s)) {
		return true;
		}

		/*
		* To avoid excessive duplication of ops we implement shift
		* by immediate using the variable shift operations.
		*/
		constimm = tcg_const_i64(dup_const(a->size, a->shift));

		for (pass = 0; pass < a->q + 1; pass++) {
		TCGv_i64 tmp = tcg_temp_new_i64();

		neon_load_reg64(tmp, a->vm + pass);
		fn(tmp, cpu_env, tmp, constimm);
		neon_store_reg64(tmp, a->vd + pass);
		}
		tcg_temp_free_i64(constimm);
		return true;
		}

		static bool do_2shift_env_32(DisasContext s, arg_2reg_shift a,
		NeonGenTwoOpEnvFn *fn)
		{
		/*
		* 2-reg-and-shift operations, size < 3 case, where the
		* helper needs to be passed cpu_env.
		*/
		TCGv_i32 constimm;
		int pass;

		if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
		return false;
		}

		/* UNDEF accesses to D16-D31 if they don't exist. */
		if (!dc_isar_feature(aa32_simd_r32, s) &&
		((a->vd \| a->vm) & 0x10)) {
		return false;
		}

		if ((a->vm \| a->vd) & a->q) {
		return false;
		}

		if (!vfp_access_check(s)) {
		return true;
		}

		/*
		* To avoid excessive duplication of ops we implement shift
		* by immediate using the variable shift operations.
		*/
		constimm = tcg_const_i32(dup_const(a->size, a->shift));

		for (pass = 0; pass < (a->q ? 4 : 2); pass++) {
		TCGv_i32 tmp = neon_load_reg(a->vm, pass);
		fn(tmp, cpu_env, tmp, constimm);
		neon_store_reg(a->vd, pass, tmp);
		}
		tcg_temp_free_i32(constimm);
		return true;
		}

		#define DO_2SHIFT_ENV(INSN, FUNC) \
		static bool trans_##INSN##_64_2sh(DisasContext s, arg_2reg_shift a) \
		{ \
		return do_2shift_env_64(s, a, gen_helper_neon_##FUNC##64); \
		} \
		static bool trans_##INSN##_2sh(DisasContext s, arg_2reg_shift a) \
		{ \
		static NeonGenTwoOpEnvFn * const fns[] = { \
		gen_helper_neon_##FUNC##8, \
		gen_helper_neon_##FUNC##16, \
		gen_helper_neon_##FUNC##32, \
		}; \
		assert(a->size < ARRAY_SIZE(fns)); \
		return do_2shift_env_32(s, a, fns[a->size]); \
		}

		DO_2SHIFT_ENV(VQSHLU, qshlu_s)
		DO_2SHIFT_ENV(VQSHL_U, qshl_u)
		DO_2SHIFT_ENV(VQSHL_S, qshl_s)

target/arm/translate.c

+3 −107

Original line number	Diff line number	Diff line
		@@ -3011,29 +3011,6 @@ static inline void gen_neon_rsb(int size, TCGv_i32 t0, TCGv_i32 t1)
		}
		}

		#define GEN_NEON_INTEGER_OP_ENV(name) do { \
		switch ((size << 1) \| u) { \
		case 0: \
		gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
		break; \
		case 1: \
		gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
		break; \
		case 2: \
		gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
		break; \
		case 3: \
		gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
		break; \
		case 4: \
		gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
		break; \
		case 5: \
		gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
		break; \
		default: return 1; \
		}} while (0)

		static TCGv_i32 neon_load_scratch(int scratch)
		{
		TCGv_i32 tmp = tcg_temp_new_i32();
		@@ -5252,7 +5229,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
		int size;
		int shift;
		int pass;
		int count;
		int u;
		int vec_size;
		uint32_t imm;
		@@ -5302,6 +5278,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
		case 3: /* VRSRA */
		case 4: /* VSRI */
		case 5: /* VSHL, VSLI */
		case 6: /* VQSHLU */
		case 7: /* VQSHL */
		return 1; /* handled by decodetree */
		default:
		break;
		@@ -5319,89 +5297,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
		size--;
		}
		shift = (insn >> 16) & ((1 << (3 + size)) - 1);
		if (op < 8) {
		/* Shift by immediate:
		VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
		if (q && ((rd \| rm) & 1)) {
		return 1;
		}
		if (!u && (op == 4 \|\| op == 6)) {
		return 1;
		}
		/* Right shifts are encoded as N - shift, where N is the
		element size in bits. */
		if (op <= 4) {
		shift = shift - (1 << (size + 3));
		}

		if (size == 3) {
		count = q + 1;
		} else {
		count = q ? 4: 2;
		}

		/* To avoid excessive duplication of ops we implement shift
		* by immediate using the variable shift operations.
		*/
		imm = dup_const(size, shift);

		for (pass = 0; pass < count; pass++) {
		if (size == 3) {
		neon_load_reg64(cpu_V0, rm + pass);
		tcg_gen_movi_i64(cpu_V1, imm);
		switch (op) {
		case 6: /* VQSHLU */
		gen_helper_neon_qshlu_s64(cpu_V0, cpu_env,
		cpu_V0, cpu_V1);
		break;
		case 7: /* VQSHL */
		if (u) {
		gen_helper_neon_qshl_u64(cpu_V0, cpu_env,
		cpu_V0, cpu_V1);
		} else {
		gen_helper_neon_qshl_s64(cpu_V0, cpu_env,
		cpu_V0, cpu_V1);
		}
		break;
		default:
		g_assert_not_reached();
		}
		neon_store_reg64(cpu_V0, rd + pass);
		} else { /* size < 3 */
		/* Operands in T0 and T1. */
		tmp = neon_load_reg(rm, pass);
		tmp2 = tcg_temp_new_i32();
		tcg_gen_movi_i32(tmp2, imm);
		switch (op) {
		case 6: /* VQSHLU */
		switch (size) {
		case 0:
		gen_helper_neon_qshlu_s8(tmp, cpu_env,
		tmp, tmp2);
		break;
		case 1:
		gen_helper_neon_qshlu_s16(tmp, cpu_env,
		tmp, tmp2);
		break;
		case 2:
		gen_helper_neon_qshlu_s32(tmp, cpu_env,
		tmp, tmp2);
		break;
		default:
		abort();
		}
		break;
		case 7: /* VQSHL */
		GEN_NEON_INTEGER_OP_ENV(qshl);
		break;
		default:
		g_assert_not_reached();
		}
		tcg_temp_free_i32(tmp2);
		neon_store_reg(rd, pass, tmp);
		}
		} /* for pass */
		} else if (op < 10) {
		if (op < 10) {
		/* Shift by immediate and narrow:
		VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
		int input_unsigned = (op == 8) ? !u : u;