Loading tcg/ppc64/tcg-target.c +34 −10 Original line number Diff line number Diff line Loading @@ -1394,17 +1394,19 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_and_i32: a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_andi32(s, args[0], args[1], args[2]); tcg_out_andi32(s, a0, a1, a2); } else { tcg_out32(s, AND | SAB(args[1], args[0], args[2])); tcg_out32(s, AND | SAB(a1, a0, a2)); } break; case INDEX_op_and_i64: a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_andi64(s, args[0], args[1], args[2]); tcg_out_andi64(s, a0, a1, a2); } else { tcg_out32(s, AND | SAB(args[1], args[0], args[2])); tcg_out32(s, AND | SAB(a1, a0, a2)); } break; case INDEX_op_or_i64: Loading @@ -1426,14 +1428,36 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; case INDEX_op_andc_i32: a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_andi32(s, a0, a1, ~a2); } else { tcg_out32(s, ANDC | SAB(a1, a0, a2)); } break; case INDEX_op_andc_i64: tcg_out32(s, ANDC | SAB(args[1], args[0], args[2])); a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_andi64(s, a0, a1, ~a2); } else { tcg_out32(s, ANDC | SAB(a1, a0, a2)); } break; case INDEX_op_orc_i32: if (const_args[2]) { tcg_out_ori32(s, args[0], args[1], ~args[2]); break; } /* FALLTHRU */ case INDEX_op_orc_i64: tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); break; case INDEX_op_eqv_i32: if (const_args[2]) { tcg_out_xori32(s, args[0], args[1], ~args[2]); break; } /* FALLTHRU */ case INDEX_op_eqv_i64: tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); break; Loading Loading @@ -1820,9 +1844,9 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_and_i32, { "r", "r", "ri" } }, { INDEX_op_or_i32, { "r", "r", "ri" } }, { INDEX_op_xor_i32, { "r", "r", "ri" } }, { INDEX_op_andc_i32, { "r", "r", "r" } }, { INDEX_op_orc_i32, { "r", "r", "r" } }, { INDEX_op_eqv_i32, { "r", "r", "r" } }, { INDEX_op_andc_i32, { "r", "r", "ri" } }, { INDEX_op_orc_i32, { "r", "r", "ri" } }, { INDEX_op_eqv_i32, { "r", "r", "ri" } }, { INDEX_op_nand_i32, { "r", "r", "r" } }, { INDEX_op_nor_i32, { "r", "r", "r" } }, Loading @@ -1840,10 +1864,10 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_add_i64, { "r", "r", "rT" } }, { INDEX_op_sub_i64, { "r", "rI", "rT" } }, { INDEX_op_and_i64, { "r", "r", "rU" } }, { INDEX_op_and_i64, { "r", "r", "ri" } }, { INDEX_op_or_i64, { "r", "r", "rU" } }, { INDEX_op_xor_i64, { "r", "r", "rU" } }, { INDEX_op_andc_i64, { "r", "r", "r" } }, { INDEX_op_andc_i64, { "r", "r", "ri" } }, { INDEX_op_orc_i64, { "r", "r", "r" } }, { INDEX_op_eqv_i64, { "r", "r", "r" } }, { INDEX_op_nand_i64, { "r", "r", "r" } }, Loading Loading
tcg/ppc64/tcg-target.c +34 −10 Original line number Diff line number Diff line Loading @@ -1394,17 +1394,19 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_and_i32: a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_andi32(s, args[0], args[1], args[2]); tcg_out_andi32(s, a0, a1, a2); } else { tcg_out32(s, AND | SAB(args[1], args[0], args[2])); tcg_out32(s, AND | SAB(a1, a0, a2)); } break; case INDEX_op_and_i64: a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_andi64(s, args[0], args[1], args[2]); tcg_out_andi64(s, a0, a1, a2); } else { tcg_out32(s, AND | SAB(args[1], args[0], args[2])); tcg_out32(s, AND | SAB(a1, a0, a2)); } break; case INDEX_op_or_i64: Loading @@ -1426,14 +1428,36 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; case INDEX_op_andc_i32: a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_andi32(s, a0, a1, ~a2); } else { tcg_out32(s, ANDC | SAB(a1, a0, a2)); } break; case INDEX_op_andc_i64: tcg_out32(s, ANDC | SAB(args[1], args[0], args[2])); a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_andi64(s, a0, a1, ~a2); } else { tcg_out32(s, ANDC | SAB(a1, a0, a2)); } break; case INDEX_op_orc_i32: if (const_args[2]) { tcg_out_ori32(s, args[0], args[1], ~args[2]); break; } /* FALLTHRU */ case INDEX_op_orc_i64: tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); break; case INDEX_op_eqv_i32: if (const_args[2]) { tcg_out_xori32(s, args[0], args[1], ~args[2]); break; } /* FALLTHRU */ case INDEX_op_eqv_i64: tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); break; Loading Loading @@ -1820,9 +1844,9 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_and_i32, { "r", "r", "ri" } }, { INDEX_op_or_i32, { "r", "r", "ri" } }, { INDEX_op_xor_i32, { "r", "r", "ri" } }, { INDEX_op_andc_i32, { "r", "r", "r" } }, { INDEX_op_orc_i32, { "r", "r", "r" } }, { INDEX_op_eqv_i32, { "r", "r", "r" } }, { INDEX_op_andc_i32, { "r", "r", "ri" } }, { INDEX_op_orc_i32, { "r", "r", "ri" } }, { INDEX_op_eqv_i32, { "r", "r", "ri" } }, { INDEX_op_nand_i32, { "r", "r", "r" } }, { INDEX_op_nor_i32, { "r", "r", "r" } }, Loading @@ -1840,10 +1864,10 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_add_i64, { "r", "r", "rT" } }, { INDEX_op_sub_i64, { "r", "rI", "rT" } }, { INDEX_op_and_i64, { "r", "r", "rU" } }, { INDEX_op_and_i64, { "r", "r", "ri" } }, { INDEX_op_or_i64, { "r", "r", "rU" } }, { INDEX_op_xor_i64, { "r", "r", "rU" } }, { INDEX_op_andc_i64, { "r", "r", "r" } }, { INDEX_op_andc_i64, { "r", "r", "ri" } }, { INDEX_op_orc_i64, { "r", "r", "r" } }, { INDEX_op_eqv_i64, { "r", "r", "r" } }, { INDEX_op_nand_i64, { "r", "r", "r" } }, Loading