Commit ce1010d6 authored by Richard Henderson's avatar Richard Henderson
Browse files

tcg-ppc64: Implement compound logicals 



Mostly copied from the ppc32 port.

Reviewed-by: default avatarAurelien Jarno <aurelien@aurel32.net>
Signed-off-by: default avatarRichard Henderson <rth@twiddle.net>
parent 68aebd45

tcg/ppc64/tcg-target.c

+34 −0
Original line number Diff line number Diff line
@@ -385,6 +385,10 @@ static int tcg_target_const_match (tcg_target_long val, 
#define NOR    XO31(124)

#define CNTLZW XO31( 26)

#define CNTLZD XO31( 58)

#define ANDC   XO31( 60)

#define ORC    XO31(412)

#define EQV    XO31(284)

#define NAND   XO31(476)



#define MULLD  XO31(233)

#define MULHD  XO31( 73)
@@ -1421,6 +1425,26 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, 
            tcg_out32(s, XOR | SAB(a1, a0, a2));

        }

        break;

    case INDEX_op_andc_i32:

    case INDEX_op_andc_i64:

        tcg_out32(s, ANDC | SAB(args[1], args[0], args[2]));

        break;

    case INDEX_op_orc_i32:

    case INDEX_op_orc_i64:

        tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));

        break;

    case INDEX_op_eqv_i32:

    case INDEX_op_eqv_i64:

        tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));

        break;

    case INDEX_op_nand_i32:

    case INDEX_op_nand_i64:

        tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));

        break;

    case INDEX_op_nor_i32:

    case INDEX_op_nor_i64:

        tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));

        break;



    case INDEX_op_mul_i32:

        if (const_args[2]) {
@@ -1796,6 +1820,11 @@ static const TCGTargetOpDef ppc_op_defs[] = { 
    { INDEX_op_and_i32, { "r", "r", "ri" } },

    { INDEX_op_or_i32, { "r", "r", "ri" } },

    { INDEX_op_xor_i32, { "r", "r", "ri" } },

    { INDEX_op_andc_i32, { "r", "r", "r" } },

    { INDEX_op_orc_i32, { "r", "r", "r" } },

    { INDEX_op_eqv_i32, { "r", "r", "r" } },

    { INDEX_op_nand_i32, { "r", "r", "r" } },

    { INDEX_op_nor_i32, { "r", "r", "r" } },



    { INDEX_op_shl_i32, { "r", "r", "ri" } },

    { INDEX_op_shr_i32, { "r", "r", "ri" } },
@@ -1814,6 +1843,11 @@ static const TCGTargetOpDef ppc_op_defs[] = { 
    { INDEX_op_and_i64, { "r", "r", "rU" } },

    { INDEX_op_or_i64, { "r", "r", "rU" } },

    { INDEX_op_xor_i64, { "r", "r", "rU" } },

    { INDEX_op_andc_i64, { "r", "r", "r" } },

    { INDEX_op_orc_i64, { "r", "r", "r" } },

    { INDEX_op_eqv_i64, { "r", "r", "r" } },

    { INDEX_op_nand_i64, { "r", "r", "r" } },

    { INDEX_op_nor_i64, { "r", "r", "r" } },



    { INDEX_op_shl_i64, { "r", "r", "ri" } },

    { INDEX_op_shr_i64, { "r", "r", "ri" } },

tcg/ppc64/tcg-target.h

+10 −10
Original line number Diff line number Diff line
@@ -83,11 +83,11 @@ typedef enum { 
#define TCG_TARGET_HAS_bswap32_i32      1

#define TCG_TARGET_HAS_not_i32          1

#define TCG_TARGET_HAS_neg_i32          1

#define TCG_TARGET_HAS_andc_i32         0

#define TCG_TARGET_HAS_orc_i32          0

#define TCG_TARGET_HAS_eqv_i32          0

#define TCG_TARGET_HAS_nand_i32         0

#define TCG_TARGET_HAS_nor_i32          0

#define TCG_TARGET_HAS_andc_i32         1

#define TCG_TARGET_HAS_orc_i32          1

#define TCG_TARGET_HAS_eqv_i32          1

#define TCG_TARGET_HAS_nand_i32         1

#define TCG_TARGET_HAS_nor_i32          1

#define TCG_TARGET_HAS_deposit_i32      0

#define TCG_TARGET_HAS_movcond_i32      0

#define TCG_TARGET_HAS_add2_i32         0
@@ -105,11 +105,11 @@ typedef enum { 
#define TCG_TARGET_HAS_bswap64_i64      1

#define TCG_TARGET_HAS_not_i64          1

#define TCG_TARGET_HAS_neg_i64          1

#define TCG_TARGET_HAS_andc_i64         0

#define TCG_TARGET_HAS_orc_i64          0

#define TCG_TARGET_HAS_eqv_i64          0

#define TCG_TARGET_HAS_nand_i64         0

#define TCG_TARGET_HAS_nor_i64          0

#define TCG_TARGET_HAS_andc_i64         1

#define TCG_TARGET_HAS_orc_i64          1

#define TCG_TARGET_HAS_eqv_i64          1

#define TCG_TARGET_HAS_nand_i64         1

#define TCG_TARGET_HAS_nor_i64          1

#define TCG_TARGET_HAS_deposit_i64      0

#define TCG_TARGET_HAS_movcond_i64      0

#define TCG_TARGET_HAS_add2_i64         0