Commit 2e3a76ae authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160404' into staging 



target-arm queue:
 * bcm2836: wire up CPU timer interrupts correctly
 * linux-user: ignore EXCP_YIELD in ARM cpu_loop()
 * target-arm: correctly reset SCTLR_EL3
 * target-arm: remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3
 * target-arm: make the 64-bit version of VTCR do the migration

# gpg: Signature made Mon 04 Apr 2016 17:42:16 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"

* remotes/pmaydell/tags/pull-target-arm-20160404:
  target-arm: Make the 64-bit version of VTCR do the migration
  target-arm: Remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3
  target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUs
  linux-user: arm: Handle (ignore) EXCP_YIELD in ARM cpu_loop()
  hw/arm/bcm2836: Wire up CPU timer interrupts correctly

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents c40e13e1 bf06c112

hw/arm/bcm2836.c

+5 −1
Original line number Diff line number Diff line
@@ -139,9 +139,13 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) 


        /* Connect timers from the CPU to the interrupt controller */

        qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_PHYS,

                qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n));

                qdev_get_gpio_in_named(DEVICE(&s->control), "cntpnsirq", n));

        qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_VIRT,

                qdev_get_gpio_in_named(DEVICE(&s->control), "cntvirq", n));

        qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_HYP,

                qdev_get_gpio_in_named(DEVICE(&s->control), "cnthpirq", n));

        qdev_connect_gpio_out(DEVICE(&s->cpus[n]), GTIMER_SEC,

                qdev_get_gpio_in_named(DEVICE(&s->control), "cntpsirq", n));

    }

}

linux-user/main.c

+6 −0
Original line number Diff line number Diff line
@@ -907,6 +907,9 @@ void cpu_loop(CPUARMState *env) 
            if (do_kernel_trap(env))

              goto error;

            break;

        case EXCP_YIELD:

            /* nothing to do here for user-mode, just resume guest code */

            break;

        default:

        error:

            EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
@@ -1097,6 +1100,9 @@ void cpu_loop(CPUARMState *env) 
        case EXCP_SEMIHOST:

            env->xregs[0] = do_arm_semihosting(env);

            break;

        case EXCP_YIELD:

            /* nothing to do here for user-mode, just resume guest code */

            break;

        default:

            EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);

            abort();

target-arm/helper.c

+18 −13
Original line number Diff line number Diff line
@@ -3509,7 +3509,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { 
      .access = PL2_RW,

      .fieldoffset = offsetof(CPUARMState, elr_el[2]) },

    { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,

      .type = ARM_CP_ALIAS,

      .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,

      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },

    { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
@@ -3565,11 +3564,15 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { 
      .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },

    { .name = "VTCR", .state = ARM_CP_STATE_AA32,

      .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,

      .type = ARM_CP_ALIAS,

      .access = PL2_RW, .accessfn = access_el3_aa32ns,

      .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },

    { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,

      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,

      .access = PL2_RW, .type = ARM_CP_ALIAS,

      .access = PL2_RW,

      /* no .writefn needed as this can't cause an ASID change;

       * no .raw_writefn or .resetfn needed as we never use mask/base_mask

       */

      .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },

    { .name = "VTTBR", .state = ARM_CP_STATE_AA32,

      .cp = 15, .opc1 = 6, .crm = 2,
@@ -3744,11 +3747,6 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { 
      .access = PL1_RW, .accessfn = access_trap_aa32s_el1,

      .writefn = vbar_write, .resetvalue = 0,

      .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },

    { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,

      .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */

      .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,

      .access = PL3_RW, .raw_writefn = raw_write, .writefn = sctlr_write,

      .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]) },

    { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,

      .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,

      .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
@@ -3764,7 +3762,6 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { 
      .access = PL3_RW,

      .fieldoffset = offsetof(CPUARMState, elr_el[3]) },

    { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,

      .type = ARM_CP_ALIAS,

      .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,

      .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },

    { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
@@ -4641,12 +4638,20 @@ void register_cp_regs_for_features(ARMCPU *cpu) 
    }

    if (arm_feature(env, ARM_FEATURE_EL3)) {

        define_arm_cp_regs(cpu, el3_cp_reginfo);

        ARMCPRegInfo rvbar = {

            .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,

        ARMCPRegInfo el3_regs[] = {

            { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,

            .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar

              .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },

            { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,

              .access = PL3_RW,

              .raw_writefn = raw_write, .writefn = sctlr_write,

              .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),

              .resetvalue = cpu->reset_sctlr },

            REGINFO_SENTINEL

        };

        define_one_arm_cp_reg(cpu, &rvbar);



        define_arm_cp_regs(cpu, el3_regs);

    }

    /* The behaviour of NSACR is sufficiently various that we don't

     * try to describe it in a single reginfo: