Commit bf06c112 authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm: Make the 64-bit version of VTCR do the migration 



Move the ALIAS tag from VTCR_EL2 to VTCR so that we migrate the
64-bit version, as is usual. (This has no particular effect now
unless the guest wrote to the high RES0 bits of VTCR_EL2.)
Add a comment about why it's OK that we don't have the various
accessor functions that the EL1 TCR regdefs do.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarSergey Fedorov <sergey.fedorov@linaro.org>
Message-id: 1459435778-5526-4-git-send-email-peter.maydell@linaro.org
parent 094a7d0b

target-arm/helper.c

+5 −1
Original line number Diff line number Diff line
@@ -3564,11 +3564,15 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { 
      .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },

    { .name = "VTCR", .state = ARM_CP_STATE_AA32,

      .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,

      .type = ARM_CP_ALIAS,

      .access = PL2_RW, .accessfn = access_el3_aa32ns,

      .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },

    { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,

      .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,

      .access = PL2_RW, .type = ARM_CP_ALIAS,

      .access = PL2_RW,

      /* no .writefn needed as this can't cause an ASID change;

       * no .raw_writefn or .resetfn needed as we never use mask/base_mask

       */

      .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },

    { .name = "VTTBR", .state = ARM_CP_STATE_AA32,

      .cp = 15, .opc1 = 6, .crm = 2,