Commit 2e1cf2c9 authored by Francisco Iglesias's avatar Francisco Iglesias Committed by Peter Maydell
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xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done 



Don't set TX FIFO UNDERFLOW interrupt after transmitting the commands.
Also update interrupts after reading out the interrupt status.

Signed-off-by: default avatarFrancisco Iglesias <frasse.iglesias@gmail.com>
Acked-by: default avatarAlistair Francis <alistair.francis@xilinx.com>
Reviewed-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20171126231634.9531-12-frasse.iglesias@gmail.com
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent fbfaa507

hw/ssi/xilinx_spips.c

+1 −3
Original line number Diff line number Diff line
@@ -329,9 +329,6 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) 
        uint8_t addr_length;



        if (fifo8_is_empty(&s->tx_fifo)) {

            if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {

                s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;

            }

            xilinx_spips_update_ixr(s);

            return;

        } else if (s->snoop_state == SNOOP_STRIPING) {
@@ -530,6 +527,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, 
        ret = s->regs[addr] & IXR_ALL;

        s->regs[addr] = 0;

        DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);

        xilinx_spips_update_ixr(s);

        return ret;

    case R_INTR_MASK:

        mask = IXR_ALL;