Commit 2a6332d9 authored by Sergey Fedorov's avatar Sergey Fedorov Committed by Peter Maydell
Browse files

target-arm: fix write helper for TLBI ALLE1IS 



TLBI ALLE1IS is an operation that does invalidate TLB entries on all PEs
in the same Inner Sharable domain, not just on the current CPU. So we
must use tlbiall_is_write() here.

Signed-off-by: default avatarSergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1435676538-31345-1-git-send-email-serge.fdrv@gmail.com
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent f50a1640

target-arm/helper.c

+1 −1
Original line number Diff line number Diff line
@@ -2441,7 +2441,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { 
    { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,

      .access = PL2_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbiall_write },

      .writefn = tlbiall_is_write },

    { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,

      .access = PL1_W, .type = ARM_CP_NO_RAW,