Commit f50a1640 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging 



# gpg: Signature made Sat Jul  4 07:06:08 2015 BST using RSA key ID AAFC390E
# gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: FAEB 9711 A12C F475 812F  18F2 88A9 064D 1835 61EB
#      Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76  CBD0 7DEF 8106 AAFC 390E

* remotes/jnsnow/tags/ide-pull-request: (35 commits)
  ahci: fix sdb fis semantics
  qtest/ahci: halted ncq migration test
  ahci: Do not map cmd_fis to generate response
  ahci: ncq migration
  ahci: add get_cmd_header helper
  ahci: add cmd header to ncq transfer state
  qtest/ahci: halted NCQ test
  ahci: correct ncq sector count
  ahci: correct types in NCQTransferState
  ahci: add rwerror=stop support for ncq
  ahci: factor ncq_finish out of ncq_cb
  ahci: refactor process_ncq_command
  ahci: assert is_ncq for process_ncq
  ahci: stash ncq command
  ide: add limit to .prepare_buf()
  qtest/ahci: ncq migration test
  qtest/ahci: simple ncq data test
  libqos/ahci: Force all NCQ commands to be LBA48
  libqos/ahci: set the NCQ tag on command_commit
  libqos/ahci: adjust expected NCQ interrupts
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 63a9294d 7c649ac5

hw/ide/ahci.c

+286 −151
Original line number Diff line number Diff line
@@ -45,11 +45,11 @@ do { \ 
} while (0)



static void check_cmd(AHCIState *s, int port);

static int handle_cmd(AHCIState *s,int port,int slot);

static int handle_cmd(AHCIState *s, int port, uint8_t slot);

static void ahci_reset_port(AHCIState *s, int port);

static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis);

static void ahci_init_d2h(AHCIDevice *ad);

static int ahci_dma_prepare_buf(IDEDMA *dma, int is_write);

static int ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit);

static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes);

static bool ahci_map_clb_address(AHCIDevice *ad);

static bool ahci_map_fis_address(AHCIDevice *ad);
@@ -106,8 +106,6 @@ static uint32_t ahci_port_read(AHCIState *s, int port, int offset) 
        val = pr->scr_err;

        break;

    case PORT_SCR_ACT:

        pr->scr_act &= ~s->dev[port].finished;

        s->dev[port].finished = 0;

        val = pr->scr_act;

        break;

    case PORT_CMD_ISSUE:
@@ -331,8 +329,7 @@ static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) 
    }

}



static uint64_t ahci_mem_read(void *opaque, hwaddr addr,

                              unsigned size)

static uint64_t ahci_mem_read_32(void *opaque, hwaddr addr)

{

    AHCIState *s = opaque;

    uint32_t val = 0;
@@ -368,6 +365,30 @@ static uint64_t ahci_mem_read(void *opaque, hwaddr addr, 
}





/**

 * AHCI 1.3 section 3 ("HBA Memory Registers")

 * Support unaligned 8/16/32 bit reads, and 64 bit aligned reads.

 * Caller is responsible for masking unwanted higher order bytes.

 */

static uint64_t ahci_mem_read(void *opaque, hwaddr addr, unsigned size)

{

    hwaddr aligned = addr & ~0x3;

    int ofst = addr - aligned;

    uint64_t lo = ahci_mem_read_32(opaque, aligned);

    uint64_t hi;



    /* if < 8 byte read does not cross 4 byte boundary */

    if (ofst + size <= 4) {

        return lo >> (ofst * 8);

    }

    g_assert_cmpint(size, >, 1);



    /* If the 64bit read is unaligned, we will produce undefined

     * results. AHCI does not support unaligned 64bit reads. */

    hi = ahci_mem_read_32(opaque, aligned + 4);

    return (hi << 32 | lo) >> (ofst * 8);

}





static void ahci_mem_write(void *opaque, hwaddr addr,

                           uint64_t val, unsigned size)
@@ -483,7 +504,7 @@ static void ahci_reg_init(AHCIState *s) 
static void check_cmd(AHCIState *s, int port)

{

    AHCIPortRegs *pr = &s->dev[port].port_regs;

    int slot;

    uint8_t slot;



    if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) {

        for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) {
@@ -558,6 +579,7 @@ static void ahci_reset_port(AHCIState *s, int port) 
    /* reset ncq queue */

    for (i = 0; i < AHCI_MAX_CMDS; i++) {

        NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[i];

        ncq_tfs->halt = false;

        if (!ncq_tfs->used) {

            continue;

        }
@@ -642,14 +664,14 @@ static void ahci_unmap_clb_address(AHCIDevice *ad) 
    ad->lst = NULL;

}



static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished)

static void ahci_write_fis_sdb(AHCIState *s, NCQTransferState *ncq_tfs)

{

    AHCIDevice *ad = &s->dev[port];

    AHCIDevice *ad = ncq_tfs->drive;

    AHCIPortRegs *pr = &ad->port_regs;

    IDEState *ide_state;

    SDBFIS *sdb_fis;



    if (!s->dev[port].res_fis ||

    if (!ad->res_fis ||

        !(pr->cmd & PORT_CMD_FIS_RX)) {

        return;

    }
@@ -659,53 +681,35 @@ static void ahci_write_fis_sdb(AHCIState *s, int port, uint32_t finished) 


    sdb_fis->type = SATA_FIS_TYPE_SDB;

    /* Interrupt pending & Notification bit */

    sdb_fis->flags = (ad->hba->control_regs.irqstatus ? (1 << 6) : 0);

    sdb_fis->flags = 0x40; /* Interrupt bit, always 1 for NCQ */

    sdb_fis->status = ide_state->status & 0x77;

    sdb_fis->error = ide_state->error;

    /* update SAct field in SDB_FIS */

    s->dev[port].finished |= finished;

    sdb_fis->payload = cpu_to_le32(ad->finished);



    /* Update shadow registers (except BSY 0x80 and DRQ 0x08) */

    pr->tfdata = (ad->port.ifs[0].error << 8) |

        (ad->port.ifs[0].status & 0x77) |

        (pr->tfdata & 0x88);

    pr->scr_act &= ~ad->finished;

    ad->finished = 0;



    /* Trigger IRQ if interrupt bit is set (which currently, it always is) */

    if (sdb_fis->flags & 0x40) {

        ahci_trigger_irq(s, ad, PORT_IRQ_SDB_FIS);

    }

}



static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len)

{

    AHCIPortRegs *pr = &ad->port_regs;

    uint8_t *pio_fis, *cmd_fis;

    uint64_t tbl_addr;

    dma_addr_t cmd_len = 0x80;

    uint8_t *pio_fis;

    IDEState *s = &ad->port.ifs[0];



    if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {

        return;

    }



    /* map cmd_fis */

    tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr);

    cmd_fis = dma_memory_map(ad->hba->as, tbl_addr, &cmd_len,

                             DMA_DIRECTION_TO_DEVICE);



    if (cmd_fis == NULL) {

        DPRINTF(ad->port_no, "dma_memory_map failed in ahci_write_fis_pio");

        ahci_trigger_irq(ad->hba, ad, PORT_IRQ_HBUS_ERR);

        return;

    }



    if (cmd_len != 0x80) {

        DPRINTF(ad->port_no,

                "dma_memory_map mapped too few bytes in ahci_write_fis_pio");

        dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len,

                         DMA_DIRECTION_TO_DEVICE, cmd_len);

        ahci_trigger_irq(ad->hba, ad, PORT_IRQ_HBUS_ERR);

        return;

    }



    pio_fis = &ad->res_fis[RES_FIS_PSFIS];



    pio_fis[0] = SATA_FIS_TYPE_PIO_SETUP;
@@ -721,8 +725,8 @@ static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len) 
    pio_fis[9] = s->hob_lcyl;

    pio_fis[10] = s->hob_hcyl;

    pio_fis[11] = 0;

    pio_fis[12] = cmd_fis[12];

    pio_fis[13] = cmd_fis[13];

    pio_fis[12] = s->nsector & 0xFF;

    pio_fis[13] = (s->nsector >> 8) & 0xFF;

    pio_fis[14] = 0;

    pio_fis[15] = s->status;

    pio_fis[16] = len & 255;
@@ -739,9 +743,6 @@ static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len) 
    }



    ahci_trigger_irq(ad->hba, ad, PORT_IRQ_PIOS_FIS);



    dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len,

                     DMA_DIRECTION_TO_DEVICE, cmd_len);

}



static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis)
@@ -749,22 +750,12 @@ static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis) 
    AHCIPortRegs *pr = &ad->port_regs;

    uint8_t *d2h_fis;

    int i;

    dma_addr_t cmd_len = 0x80;

    int cmd_mapped = 0;

    IDEState *s = &ad->port.ifs[0];



    if (!ad->res_fis || !(pr->cmd & PORT_CMD_FIS_RX)) {

        return;

    }



    if (!cmd_fis) {

        /* map cmd_fis */

        uint64_t tbl_addr = le64_to_cpu(ad->cur_cmd->tbl_addr);

        cmd_fis = dma_memory_map(ad->hba->as, tbl_addr, &cmd_len,

                                 DMA_DIRECTION_TO_DEVICE);

        cmd_mapped = 1;

    }



    d2h_fis = &ad->res_fis[RES_FIS_RFIS];



    d2h_fis[0] = SATA_FIS_TYPE_REGISTER_D2H;
@@ -780,8 +771,8 @@ static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis) 
    d2h_fis[9] = s->hob_lcyl;

    d2h_fis[10] = s->hob_hcyl;

    d2h_fis[11] = 0;

    d2h_fis[12] = cmd_fis[12];

    d2h_fis[13] = cmd_fis[13];

    d2h_fis[12] = s->nsector & 0xFF;

    d2h_fis[13] = (s->nsector >> 8) & 0xFF;

    for (i = 14; i < 20; i++) {

        d2h_fis[i] = 0;

    }
@@ -795,26 +786,22 @@ static void ahci_write_fis_d2h(AHCIDevice *ad, uint8_t *cmd_fis) 
    }



    ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS);



    if (cmd_mapped) {

        dma_memory_unmap(ad->hba->as, cmd_fis, cmd_len,

                         DMA_DIRECTION_TO_DEVICE, cmd_len);

    }

}



static int prdt_tbl_entry_size(const AHCI_SG *tbl)

{

    /* flags_size is zero-based */

    return (le32_to_cpu(tbl->flags_size) & AHCI_PRDT_SIZE_MASK) + 1;

}



static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist,

                                int32_t offset)

                                AHCICmdHdr *cmd, int64_t limit, int32_t offset)

{

    AHCICmdHdr *cmd = ad->cur_cmd;

    uint32_t opts = le32_to_cpu(cmd->opts);

    uint64_t prdt_addr = le64_to_cpu(cmd->tbl_addr) + 0x80;

    int sglist_alloc_hint = opts >> AHCI_CMD_HDR_PRDT_LEN;

    dma_addr_t prdt_len = (sglist_alloc_hint * sizeof(AHCI_SG));

    uint16_t opts = le16_to_cpu(cmd->opts);

    uint16_t prdtl = le16_to_cpu(cmd->prdtl);

    uint64_t cfis_addr = le64_to_cpu(cmd->tbl_addr);

    uint64_t prdt_addr = cfis_addr + 0x80;

    dma_addr_t prdt_len = (prdtl * sizeof(AHCI_SG));

    dma_addr_t real_prdt_len = prdt_len;

    uint8_t *prdt;

    int i;
@@ -834,7 +821,7 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, 
     * request for sector sizes up to 32K.

     */



    if (!sglist_alloc_hint) {

    if (!prdtl) {

        DPRINTF(ad->port_no, "no sg list given by guest: 0x%08x\n", opts);

        return -1;

    }
@@ -853,13 +840,12 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, 
    }



    /* Get entries in the PRDT, init a qemu sglist accordingly */

    if (sglist_alloc_hint > 0) {

    if (prdtl > 0) {

        AHCI_SG *tbl = (AHCI_SG *)prdt;

        sum = 0;

        for (i = 0; i < sglist_alloc_hint; i++) {

            /* flags_size is zero-based */

        for (i = 0; i < prdtl; i++) {

            tbl_entry_size = prdt_tbl_entry_size(&tbl[i]);

            if (offset <= (sum + tbl_entry_size)) {

            if (offset < (sum + tbl_entry_size)) {

                off_idx = i;

                off_pos = offset - sum;

                break;
@@ -874,15 +860,16 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGList *sglist, 
            goto out;

        }



        qemu_sglist_init(sglist, qbus->parent, (sglist_alloc_hint - off_idx),

        qemu_sglist_init(sglist, qbus->parent, (prdtl - off_idx),

                         ad->hba->as);

        qemu_sglist_add(sglist, le64_to_cpu(tbl[off_idx].addr) + off_pos,

                        prdt_tbl_entry_size(&tbl[off_idx]) - off_pos);

                        MIN(prdt_tbl_entry_size(&tbl[off_idx]) - off_pos,

                            limit));



        for (i = off_idx + 1; i < sglist_alloc_hint; i++) {

            /* flags_size is zero-based */

        for (i = off_idx + 1; i < prdtl && sglist->size < limit; i++) {

            qemu_sglist_add(sglist, le64_to_cpu(tbl[i].addr),

                            prdt_tbl_entry_size(&tbl[i]));

                            MIN(prdt_tbl_entry_size(&tbl[i]),

                                limit - sglist->size));

            if (sglist->size > INT32_MAX) {

                error_report("AHCI Physical Region Descriptor Table describes "

                             "more than 2 GiB.\n");
@@ -899,28 +886,25 @@ out: 
    return r;

}



static void ncq_cb(void *opaque, int ret)

static void ncq_err(NCQTransferState *ncq_tfs)

{

    NCQTransferState *ncq_tfs = (NCQTransferState *)opaque;

    IDEState *ide_state = &ncq_tfs->drive->port.ifs[0];



    if (ret == -ECANCELED) {

        return;

    }

    /* Clear bit for this tag in SActive */

    ncq_tfs->drive->port_regs.scr_act &= ~(1 << ncq_tfs->tag);



    if (ret < 0) {

        /* error */

    ide_state->error = ABRT_ERR;

    ide_state->status = READY_STAT | ERR_STAT;

    ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag);

    } else {

        ide_state->status = READY_STAT | SEEK_STAT;

}



    ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs->drive->port_no,

                       (1 << ncq_tfs->tag));

static void ncq_finish(NCQTransferState *ncq_tfs)

{

    /* If we didn't error out, set our finished bit. Errored commands

     * do not get a bit set for the SDB FIS ACT register, nor do they

     * clear the outstanding bit in scr_act (PxSACT). */

    if (!(ncq_tfs->drive->port_regs.scr_err & (1 << ncq_tfs->tag))) {

        ncq_tfs->drive->finished |= (1 << ncq_tfs->tag);

    }



    ahci_write_fis_sdb(ncq_tfs->drive->hba, ncq_tfs);



    DPRINTF(ncq_tfs->drive->port_no, "NCQ transfer tag %d finished\n",

            ncq_tfs->tag);
@@ -931,6 +915,35 @@ static void ncq_cb(void *opaque, int ret) 
    ncq_tfs->used = 0;

}



static void ncq_cb(void *opaque, int ret)

{

    NCQTransferState *ncq_tfs = (NCQTransferState *)opaque;

    IDEState *ide_state = &ncq_tfs->drive->port.ifs[0];



    if (ret == -ECANCELED) {

        return;

    }



    if (ret < 0) {

        bool is_read = ncq_tfs->cmd == READ_FPDMA_QUEUED;

        BlockErrorAction action = blk_get_error_action(ide_state->blk,

                                                       is_read, -ret);

        if (action == BLOCK_ERROR_ACTION_STOP) {

            ncq_tfs->halt = true;

            ide_state->bus->error_status = IDE_RETRY_HBA;

        } else if (action == BLOCK_ERROR_ACTION_REPORT) {

            ncq_err(ncq_tfs);

        }

        blk_error_action(ide_state->blk, action, is_read, -ret);

    } else {

        ide_state->status = READY_STAT | SEEK_STAT;

    }



    if (!ncq_tfs->halt) {

        ncq_finish(ncq_tfs);

    }

}



static int is_ncq(uint8_t ata_cmd)

{

    /* Based on SATA 3.2 section 13.6.3.2 */
@@ -946,13 +959,60 @@ static int is_ncq(uint8_t ata_cmd) 
    }

}



static void execute_ncq_command(NCQTransferState *ncq_tfs)

{

    AHCIDevice *ad = ncq_tfs->drive;

    IDEState *ide_state = &ad->port.ifs[0];

    int port = ad->port_no;



    g_assert(is_ncq(ncq_tfs->cmd));

    ncq_tfs->halt = false;



    switch (ncq_tfs->cmd) {

    case READ_FPDMA_QUEUED:

        DPRINTF(port, "NCQ reading %d sectors from LBA %"PRId64", tag %d\n",

                ncq_tfs->sector_count, ncq_tfs->lba, ncq_tfs->tag);



        DPRINTF(port, "tag %d aio read %"PRId64"\n",

                ncq_tfs->tag, ncq_tfs->lba);



        dma_acct_start(ide_state->blk, &ncq_tfs->acct,

                       &ncq_tfs->sglist, BLOCK_ACCT_READ);

        ncq_tfs->aiocb = dma_blk_read(ide_state->blk, &ncq_tfs->sglist,

                                      ncq_tfs->lba, ncq_cb, ncq_tfs);

        break;

    case WRITE_FPDMA_QUEUED:

        DPRINTF(port, "NCQ writing %d sectors to LBA %"PRId64", tag %d\n",

                ncq_tfs->sector_count, ncq_tfs->lba, ncq_tfs->tag);



        DPRINTF(port, "tag %d aio write %"PRId64"\n",

                ncq_tfs->tag, ncq_tfs->lba);



        dma_acct_start(ide_state->blk, &ncq_tfs->acct,

                       &ncq_tfs->sglist, BLOCK_ACCT_WRITE);

        ncq_tfs->aiocb = dma_blk_write(ide_state->blk, &ncq_tfs->sglist,

                                       ncq_tfs->lba, ncq_cb, ncq_tfs);

        break;

    default:

        DPRINTF(port, "error: unsupported NCQ command (0x%02x) received\n",

                ncq_tfs->cmd);

        qemu_sglist_destroy(&ncq_tfs->sglist);

        ncq_err(ncq_tfs);

    }

}





static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis,

                                int slot)

                                uint8_t slot)

{

    AHCIDevice *ad = &s->dev[port];

    IDEState *ide_state = &ad->port.ifs[0];

    NCQFrame *ncq_fis = (NCQFrame*)cmd_fis;

    uint8_t tag = ncq_fis->tag >> 3;

    NCQTransferState *ncq_tfs = &s->dev[port].ncq_tfs[tag];

    NCQTransferState *ncq_tfs = &ad->ncq_tfs[tag];

    size_t size;



    g_assert(is_ncq(ncq_fis->command));

    if (ncq_tfs->used) {

        /* error - already in use */

        fprintf(stderr, "%s: tag %d already used\n", __FUNCTION__, tag);
@@ -960,75 +1020,82 @@ static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis, 
    }



    ncq_tfs->used = 1;

    ncq_tfs->drive = &s->dev[port];

    ncq_tfs->drive = ad;

    ncq_tfs->slot = slot;

    ncq_tfs->cmdh = &((AHCICmdHdr *)ad->lst)[slot];

    ncq_tfs->cmd = ncq_fis->command;

    ncq_tfs->lba = ((uint64_t)ncq_fis->lba5 << 40) |

                   ((uint64_t)ncq_fis->lba4 << 32) |

                   ((uint64_t)ncq_fis->lba3 << 24) |

                   ((uint64_t)ncq_fis->lba2 << 16) |

                   ((uint64_t)ncq_fis->lba1 << 8) |

                   (uint64_t)ncq_fis->lba0;



    /* Note: We calculate the sector count, but don't currently rely on it.

     * The total size of the DMA buffer tells us the transfer size instead. */

    ncq_tfs->sector_count = ((uint16_t)ncq_fis->sector_count_high << 8) |

                                ncq_fis->sector_count_low;



    DPRINTF(port, "NCQ transfer LBA from %"PRId64" to %"PRId64", "

            "drive max %"PRId64"\n",

            ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 2,

            s->dev[port].port.ifs[0].nb_sectors - 1);



    ahci_populate_sglist(&s->dev[port], &ncq_tfs->sglist, 0);

    ncq_tfs->tag = tag;



    switch(ncq_fis->command) {

        case READ_FPDMA_QUEUED:

            DPRINTF(port, "NCQ reading %d sectors from LBA %"PRId64", "

                    "tag %d\n",

                    ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag);

    /* Sanity-check the NCQ packet */

    if (tag != slot) {

        DPRINTF(port, "Warn: NCQ slot (%d) did not match the given tag (%d)\n",

                slot, tag);

    }



            DPRINTF(port, "tag %d aio read %"PRId64"\n",

                    ncq_tfs->tag, ncq_tfs->lba);

    if (ncq_fis->aux0 || ncq_fis->aux1 || ncq_fis->aux2 || ncq_fis->aux3) {

        DPRINTF(port, "Warn: Attempt to use NCQ auxiliary fields.\n");

    }

    if (ncq_fis->prio || ncq_fis->icc) {

        DPRINTF(port, "Warn: Unsupported attempt to use PRIO/ICC fields\n");

    }

    if (ncq_fis->fua & NCQ_FIS_FUA_MASK) {

        DPRINTF(port, "Warn: Unsupported attempt to use Force Unit Access\n");

    }

    if (ncq_fis->tag & NCQ_FIS_RARC_MASK) {

        DPRINTF(port, "Warn: Unsupported attempt to use Rebuild Assist\n");

    }



            dma_acct_start(ncq_tfs->drive->port.ifs[0].blk, &ncq_tfs->acct,

                           &ncq_tfs->sglist, BLOCK_ACCT_READ);

            ncq_tfs->aiocb = dma_blk_read(ncq_tfs->drive->port.ifs[0].blk,

                                          &ncq_tfs->sglist, ncq_tfs->lba,

                                          ncq_cb, ncq_tfs);

            break;

        case WRITE_FPDMA_QUEUED:

            DPRINTF(port, "NCQ writing %d sectors to LBA %"PRId64", tag %d\n",

                    ncq_tfs->sector_count-1, ncq_tfs->lba, ncq_tfs->tag);

    ncq_tfs->sector_count = ((ncq_fis->sector_count_high << 8) |

                             ncq_fis->sector_count_low);

    if (!ncq_tfs->sector_count) {

        ncq_tfs->sector_count = 0x10000;

    }

    size = ncq_tfs->sector_count * 512;

    ahci_populate_sglist(ad, &ncq_tfs->sglist, ncq_tfs->cmdh, size, 0);



            DPRINTF(port, "tag %d aio write %"PRId64"\n",

                    ncq_tfs->tag, ncq_tfs->lba);

    if (ncq_tfs->sglist.size < size) {

        error_report("ahci: PRDT length for NCQ command (0x%zx) "

                     "is smaller than the requested size (0x%zx)",

                     ncq_tfs->sglist.size, size);

        qemu_sglist_destroy(&ncq_tfs->sglist);

        ncq_err(ncq_tfs);

        ahci_trigger_irq(ad->hba, ad, PORT_IRQ_OVERFLOW);

        return;

    } else if (ncq_tfs->sglist.size != size) {

        DPRINTF(port, "Warn: PRDTL (0x%zx)"

                " does not match requested size (0x%zx)",

                ncq_tfs->sglist.size, size);

    }



            dma_acct_start(ncq_tfs->drive->port.ifs[0].blk, &ncq_tfs->acct,

                           &ncq_tfs->sglist, BLOCK_ACCT_WRITE);

            ncq_tfs->aiocb = dma_blk_write(ncq_tfs->drive->port.ifs[0].blk,

                                           &ncq_tfs->sglist, ncq_tfs->lba,

                                           ncq_cb, ncq_tfs);

            break;

        default:

            if (is_ncq(cmd_fis[2])) {

                DPRINTF(port,

                        "error: unsupported NCQ command (0x%02x) received\n",

                        cmd_fis[2]);

            } else {

                DPRINTF(port,

                        "error: tried to process non-NCQ command as NCQ\n");

    DPRINTF(port, "NCQ transfer LBA from %"PRId64" to %"PRId64", "

            "drive max %"PRId64"\n",

            ncq_tfs->lba, ncq_tfs->lba + ncq_tfs->sector_count - 1,

            ide_state->nb_sectors - 1);



    execute_ncq_command(ncq_tfs);

}

            qemu_sglist_destroy(&ncq_tfs->sglist);



static AHCICmdHdr *get_cmd_header(AHCIState *s, uint8_t port, uint8_t slot)

{

    if (port >= s->ports || slot >= AHCI_MAX_CMDS) {

        return NULL;

    }



    return s->dev[port].lst ? &((AHCICmdHdr *)s->dev[port].lst)[slot] : NULL;

}



static void handle_reg_h2d_fis(AHCIState *s, int port,

                               int slot, uint8_t *cmd_fis)

                               uint8_t slot, uint8_t *cmd_fis)

{

    IDEState *ide_state = &s->dev[port].port.ifs[0];

    AHCICmdHdr *cmd = s->dev[port].cur_cmd;

    uint32_t opts = le32_to_cpu(cmd->opts);

    AHCICmdHdr *cmd = get_cmd_header(s, port, slot);

    uint16_t opts = le16_to_cpu(cmd->opts);



    if (cmd_fis[1] & 0x0F) {

        DPRINTF(port, "Port Multiplier not supported."
@@ -1108,7 +1175,7 @@ static void handle_reg_h2d_fis(AHCIState *s, int port, 
    ide_exec_cmd(&s->dev[port].port, cmd_fis[2]);

}



static int handle_cmd(AHCIState *s, int port, int slot)

static int handle_cmd(AHCIState *s, int port, uint8_t slot)

{

    IDEState *ide_state;

    uint64_t tbl_addr;
@@ -1126,7 +1193,7 @@ static int handle_cmd(AHCIState *s, int port, int slot) 
        DPRINTF(port, "error: lst not given but cmd handled");

        return -1;

    }

    cmd = &((AHCICmdHdr *)s->dev[port].lst)[slot];

    cmd = get_cmd_header(s, port, slot);

    /* remember current slot handle for later */

    s->dev[port].cur_cmd = cmd;
@@ -1185,7 +1252,7 @@ static void ahci_start_transfer(IDEDMA *dma) 
    IDEState *s = &ad->port.ifs[0];

    uint32_t size = (uint32_t)(s->data_end - s->data_ptr);

    /* write == ram -> device */

    uint32_t opts = le32_to_cpu(ad->cur_cmd->opts);

    uint16_t opts = le16_to_cpu(ad->cur_cmd->opts);

    int is_write = opts & AHCI_CMD_WRITE;

    int is_atapi = opts & AHCI_CMD_ATAPI;

    int has_sglist = 0;
@@ -1197,7 +1264,7 @@ static void ahci_start_transfer(IDEDMA *dma) 
        goto out;

    }



    if (ahci_dma_prepare_buf(dma, is_write)) {

    if (ahci_dma_prepare_buf(dma, size)) {

        has_sglist = 1;

    }
@@ -1242,17 +1309,35 @@ static void ahci_restart_dma(IDEDMA *dma) 
    /* Nothing to do, ahci_start_dma already resets s->io_buffer_offset.  */

}



/**

 * IDE/PIO restarts are handled by the core layer, but NCQ commands

 * need an extra kick from the AHCI HBA.

 */

static void ahci_restart(IDEDMA *dma)

{

    AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);

    int i;



    for (i = 0; i < AHCI_MAX_CMDS; i++) {

        NCQTransferState *ncq_tfs = &ad->ncq_tfs[i];

        if (ncq_tfs->halt) {

            execute_ncq_command(ncq_tfs);

        }

    }

}



/**

 * Called in DMA R/W chains to read the PRDT, utilizing ahci_populate_sglist.

 * Not currently invoked by PIO R/W chains,

 * which invoke ahci_populate_sglist via ahci_start_transfer.

 */

static int32_t ahci_dma_prepare_buf(IDEDMA *dma, int is_write)

static int32_t ahci_dma_prepare_buf(IDEDMA *dma, int32_t limit)

{

    AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma);

    IDEState *s = &ad->port.ifs[0];



    if (ahci_populate_sglist(ad, &s->sg, s->io_buffer_offset) == -1) {

    if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd,

                             limit, s->io_buffer_offset) == -1) {

        DPRINTF(ad->port_no, "ahci_dma_prepare_buf failed.\n");

        return -1;

    }
@@ -1287,7 +1372,7 @@ static int ahci_dma_rw_buf(IDEDMA *dma, int is_write) 
    uint8_t *p = s->io_buffer + s->io_buffer_index;

    int l = s->io_buffer_size - s->io_buffer_index;



    if (ahci_populate_sglist(ad, &s->sg, s->io_buffer_offset)) {

    if (ahci_populate_sglist(ad, &s->sg, ad->cur_cmd, l, s->io_buffer_offset)) {

        return 0;

    }
@@ -1330,6 +1415,7 @@ static void ahci_irq_set(void *opaque, int n, int level) 


static const IDEDMAOps ahci_dma_ops = {

    .start_dma = ahci_start_dma,

    .restart = ahci_restart,

    .restart_dma = ahci_restart_dma,

    .start_transfer = ahci_start_transfer,

    .prepare_buf = ahci_dma_prepare_buf,
@@ -1400,6 +1486,21 @@ void ahci_reset(AHCIState *s) 
    }

}



static const VMStateDescription vmstate_ncq_tfs = {

    .name = "ncq state",

    .version_id = 1,

    .fields = (VMStateField[]) {

        VMSTATE_UINT32(sector_count, NCQTransferState),

        VMSTATE_UINT64(lba, NCQTransferState),

        VMSTATE_UINT8(tag, NCQTransferState),

        VMSTATE_UINT8(cmd, NCQTransferState),

        VMSTATE_UINT8(slot, NCQTransferState),

        VMSTATE_BOOL(used, NCQTransferState),

        VMSTATE_BOOL(halt, NCQTransferState),

        VMSTATE_END_OF_LIST()

    },

};



static const VMStateDescription vmstate_ahci_device = {

    .name = "ahci port",

    .version_id = 1,
@@ -1425,14 +1526,17 @@ static const VMStateDescription vmstate_ahci_device = { 
        VMSTATE_BOOL(done_atapi_packet, AHCIDevice),

        VMSTATE_INT32(busy_slot, AHCIDevice),

        VMSTATE_BOOL(init_d2h_sent, AHCIDevice),

        VMSTATE_STRUCT_ARRAY(ncq_tfs, AHCIDevice, AHCI_MAX_CMDS,

                             1, vmstate_ncq_tfs, NCQTransferState),

        VMSTATE_END_OF_LIST()

    },

};



static int ahci_state_post_load(void *opaque, int version_id)

{

    int i;

    int i, j;

    struct AHCIDevice *ad;

    NCQTransferState *ncq_tfs;

    AHCIState *s = opaque;



    for (i = 0; i < s->ports; i++) {
@@ -1444,6 +1548,37 @@ static int ahci_state_post_load(void *opaque, int version_id) 
            return -1;

        }



        for (j = 0; j < AHCI_MAX_CMDS; j++) {

            ncq_tfs = &ad->ncq_tfs[j];

            ncq_tfs->drive = ad;



            if (ncq_tfs->used != ncq_tfs->halt) {

                return -1;

            }

            if (!ncq_tfs->halt) {

                continue;

            }

            if (!is_ncq(ncq_tfs->cmd)) {

                return -1;

            }

            if (ncq_tfs->slot != ncq_tfs->tag) {

                return -1;

            }

            /* If ncq_tfs->halt is justly set, the engine should be engaged,

             * and the command list buffer should be mapped. */

            ncq_tfs->cmdh = get_cmd_header(s, i, ncq_tfs->slot);

            if (!ncq_tfs->cmdh) {

                return -1;

            }

            ahci_populate_sglist(ncq_tfs->drive, &ncq_tfs->sglist,

                                 ncq_tfs->cmdh, ncq_tfs->sector_count * 512,

                                 0);

            if (ncq_tfs->sector_count != ncq_tfs->sglist.size >> 9) {

                return -1;

            }

        }





        /*

         * If an error is present, ad->busy_slot will be valid and not -1.

         * In this case, an operation is waiting to resume and will re-check
@@ -1460,7 +1595,7 @@ static int ahci_state_post_load(void *opaque, int version_id) 
            if (ad->busy_slot < 0 || ad->busy_slot >= AHCI_MAX_CMDS) {

                return -1;

            }

            ad->cur_cmd = &((AHCICmdHdr *)ad->lst)[ad->busy_slot];

            ad->cur_cmd = get_cmd_header(s, i, ad->busy_slot);

        }

    }

hw/ide/ahci.h

+33 −14

File changed.

Preview size limit exceeded, changes collapsed.

hw/ide/core.c

+11 −4

File changed.

Preview size limit exceeded, changes collapsed.

hw/ide/internal.h

+3 −1
Original line number Diff line number Diff line
@@ -324,7 +324,7 @@ typedef void EndTransferFunc(IDEState *); 
typedef void DMAStartFunc(IDEDMA *, IDEState *, BlockCompletionFunc *);

typedef void DMAVoidFunc(IDEDMA *);

typedef int DMAIntFunc(IDEDMA *, int);

typedef int32_t DMAInt32Func(IDEDMA *, int);

typedef int32_t DMAInt32Func(IDEDMA *, int32_t len);

typedef void DMAu32Func(IDEDMA *, uint32_t);

typedef void DMAStopFunc(IDEDMA *, bool);

typedef void DMARestartFunc(void *, int, RunState);
@@ -436,6 +436,7 @@ struct IDEDMAOps { 
    DMAInt32Func *prepare_buf;

    DMAu32Func *commit_buf;

    DMAIntFunc *rw_buf;

    DMAVoidFunc *restart;

    DMAVoidFunc *restart_dma;

    DMAStopFunc *set_inactive;

    DMAVoidFunc *cmd_done;
@@ -499,6 +500,7 @@ struct IDEDevice { 
#define IDE_RETRY_READ  0x20

#define IDE_RETRY_FLUSH 0x40

#define IDE_RETRY_TRIM 0x80

#define IDE_RETRY_HBA  0x100



static inline IDEState *idebus_active_if(IDEBus *bus)

{

hw/ide/macio.c

+1 −1

File changed.

Preview size limit exceeded, changes collapsed.