Commit 2a122435 authored by Anton Blanchard's avatar Anton Blanchard Committed by David Gibson
Browse files

target/ppc: Fix lxvw4x, lxvh8x and lxvb16x 



During the conversion these instructions were incorrectly treated as
stores. We need to use set_cpu_vsr* and not get_cpu_vsr*.

Fixes: 8b3b2d75 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for VSR register access")
Signed-off-by: default avatarAnton Blanchard <anton@ozlabs.org>
Reviewed-by: default avatarMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tested-by: default avatarGreg Kurz <groug@kaod.org>
Reviewed-by: default avatarGreg Kurz <groug@kaod.org>
Message-Id: <20190524065345.25591-1-mark.cave-ayland@ilande.co.uk>
Signed-off-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
parent 70282930

target/ppc/translate/vsx-impl.inc.c

+7 −6
Original line number Diff line number Diff line
@@ -102,8 +102,7 @@ static void gen_lxvw4x(DisasContext *ctx) 
    }

    xth = tcg_temp_new_i64();

    xtl = tcg_temp_new_i64();

    get_cpu_vsrh(xth, xT(ctx->opcode));

    get_cpu_vsrl(xtl, xT(ctx->opcode));



    gen_set_access_type(ctx, ACCESS_INT);

    EA = tcg_temp_new();
@@ -126,6 +125,8 @@ static void gen_lxvw4x(DisasContext *ctx) 
        tcg_gen_addi_tl(EA, EA, 8);

        tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);

    }

    set_cpu_vsrh(xT(ctx->opcode), xth);

    set_cpu_vsrl(xT(ctx->opcode), xtl);

    tcg_temp_free(EA);

    tcg_temp_free_i64(xth);

    tcg_temp_free_i64(xtl);
@@ -185,8 +186,6 @@ static void gen_lxvh8x(DisasContext *ctx) 
    }

    xth = tcg_temp_new_i64();

    xtl = tcg_temp_new_i64();

    get_cpu_vsrh(xth, xT(ctx->opcode));

    get_cpu_vsrl(xtl, xT(ctx->opcode));

    gen_set_access_type(ctx, ACCESS_INT);



    EA = tcg_temp_new();
@@ -197,6 +196,8 @@ static void gen_lxvh8x(DisasContext *ctx) 
    if (ctx->le_mode) {

        gen_bswap16x8(xth, xtl, xth, xtl);

    }

    set_cpu_vsrh(xT(ctx->opcode), xth);

    set_cpu_vsrl(xT(ctx->opcode), xtl);

    tcg_temp_free(EA);

    tcg_temp_free_i64(xth);

    tcg_temp_free_i64(xtl);
@@ -214,14 +215,14 @@ static void gen_lxvb16x(DisasContext *ctx) 
    }

    xth = tcg_temp_new_i64();

    xtl = tcg_temp_new_i64();

    get_cpu_vsrh(xth, xT(ctx->opcode));

    get_cpu_vsrl(xtl, xT(ctx->opcode));

    gen_set_access_type(ctx, ACCESS_INT);

    EA = tcg_temp_new();

    gen_addr_reg_index(ctx, EA);

    tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ);

    tcg_gen_addi_tl(EA, EA, 8);

    tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);

    set_cpu_vsrh(xT(ctx->opcode), xth);

    set_cpu_vsrl(xT(ctx->opcode), xtl);

    tcg_temp_free(EA);

    tcg_temp_free_i64(xth);

    tcg_temp_free_i64(xtl);