Commit 2900847f authored Feb 15, 2019 by Richard Henderson Committed by Peter Maydell Feb 15, 2019

target/arm: Rely on optimization within tcg_gen_gvec_or



Since we're now handling a == b generically, we no longer need
to do it by hand within target/arm/.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190209033847.9014-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

parent 5007c904

target/arm/translate-a64.c

+1 −5

Original line number	Diff line number	Diff line
		@@ -10648,11 +10648,7 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
		gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0);
		return;
		case 2: /* ORR */
		if (rn == rm) { /* MOV */
		gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_mov, 0);
		} else {
		gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0);
		}
		return;
		case 3: /* ORN */
		gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0);

target/arm/translate-sve.c

+1 −5

Original line number	Diff line number	Diff line
		@@ -280,12 +280,8 @@ static bool trans_AND_zzz(DisasContext s, arg_rrr_esz a)

		static bool trans_ORR_zzz(DisasContext s, arg_rrr_esz a)
		{
		if (a->rn == a->rm) { /* MOV */
		return do_mov_z(s, a->rd, a->rn);
		} else {
		return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
		}
		}

		static bool trans_EOR_zzz(DisasContext s, arg_rrr_esz a)
		{

target/arm/translate.c

+3 −9

Original line number	Diff line number	Diff line
		@@ -6294,15 +6294,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
		tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs,
		vec_size, vec_size);
		break;
		case 2:
		if (rn == rm) {
		/* VMOV */
		tcg_gen_gvec_mov(0, rd_ofs, rn_ofs, vec_size, vec_size);
		} else {
		/* VORR */
		case 2: /* VORR */
		tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs,
		vec_size, vec_size);
		}
		break;
		case 3: /* VORN */
		tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs,