Commit 21317bc2 authored by Andreas Färber's avatar Andreas Färber
Browse files

target-cris/helper.c: Update Coding Style 



Reindent, add missing braces and drop/adjust whitespace.

Prepares for CPUArchState-to-CPUState field movements in
cpu_cris_handle_mmu_fault(), do_interruptv10() and do_interrupt().
The remaining functions were so minor that they can be fixed in one go.

Acked-by: default avatarEdgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
parent f56e3a14

target-cris/helper.c

+196 −197
Original line number Diff line number Diff line
@@ -74,21 +74,19 @@ int cpu_cris_handle_mmu_fault (CPUCRISState *env, target_ulong address, int rw, 
    D(printf("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));

    miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,

                              rw, mmu_idx, 0);

	if (miss)

	{

		if (env->exception_index == EXCP_BUSFAULT)

    if (miss) {

        if (env->exception_index == EXCP_BUSFAULT) {

            cpu_abort(env,

                      "CRIS: Illegal recursive bus fault."

                      "addr=%x rw=%d\n",

                      address, rw);

        }



        env->pregs[PR_EDA] = address;

        env->exception_index = EXCP_BUSFAULT;

        env->fault_vector = res.bf_vec;

        r = 1;

	}

	else

	{

    } else {

        /*

         * Mask off the cache selection bit. The ETRAX busses do not

         * see the top bit.
@@ -99,10 +97,11 @@ int cpu_cris_handle_mmu_fault (CPUCRISState *env, target_ulong address, int rw, 
                     prot, mmu_idx, TARGET_PAGE_SIZE);

        r = 0;

    }

	if (r > 0)

    if (r > 0) {

        D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n",

              __func__, r, env->interrupt_request, address, res.phy,

              res.bf_vec, env->pc);

    }

    return r;

}
@@ -115,8 +114,7 @@ static void do_interruptv10(CPUCRISState *env) 
          env->interrupt_request);



    assert(!(env->pregs[PR_CCS] & PFIX_FLAG));

	switch (env->exception_index)

	{

    switch (env->exception_index) {

    case EXCP_BREAK:

        /* These exceptions are genereated by the core itself.

           ERP should point to the insn following the brk.  */
@@ -166,15 +164,15 @@ void do_interrupt(CPUCRISState *env) 
{

    int ex_vec = -1;



	if (env->pregs[PR_VR] < 32)

    if (env->pregs[PR_VR] < 32) {

        return do_interruptv10(env);

    }



    D_LOG("exception index=%d interrupt_req=%d\n",

          env->exception_index,

          env->interrupt_request);



	switch (env->exception_index)

	{

    switch (env->exception_index) {

    case EXCP_BREAK:

        /* These exceptions are genereated by the core itself.

           ERP should point to the insn following the brk.  */
@@ -258,8 +256,9 @@ hwaddr cpu_get_phys_page_debug(CPUCRISState * env, target_ulong addr) 
        miss = cris_mmu_translate(&res, env, addr, 2, 0, 1);

    }



	if (!miss)

    if (!miss) {

        phy = res.phy;

    }

    D(fprintf(stderr, "%s %x -> %x\n", __func__, addr, phy));

    return phy;

}