Commit f56e3a14 authored by Andreas Färber's avatar Andreas Färber
Browse files

target-i386: Update VMStateDescription to X86CPU 



Expose vmstate_cpu as vmstate_x86_cpu and hook it up to CPUClass::vmsd.
Adapt opaques and VMState fields to X86CPU. Drop cpu_{save,load}().

Reviewed-by: default avatarEduardo Habkost <ehabkost@redhat.com>
Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
parent ca91b15f

target-i386/cpu-qom.h

+4 −0
Original line number Diff line number Diff line
@@ -76,4 +76,8 @@ static inline X86CPU *x86_env_get_cpu(CPUX86State *env) 


#define ENV_OFFSET offsetof(X86CPU, env)



#ifndef CONFIG_USER_ONLY

extern const struct VMStateDescription vmstate_x86_cpu;

#endif



#endif

target-i386/cpu.c

+2 −0
Original line number Diff line number Diff line
@@ -2250,6 +2250,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 


    xcc->parent_reset = cc->reset;

    cc->reset = x86_cpu_reset;



    cpu_class_set_vmsd(cc, &vmstate_x86_cpu);

}



static const TypeInfo x86_cpu_type_info = {

target-i386/cpu.h

+0 −2
Original line number Diff line number Diff line
@@ -1092,8 +1092,6 @@ static inline CPUX86State *cpu_init(const char *cpu_model) 
#define cpu_list x86_cpu_list

#define cpudef_setup	x86_cpudef_setup



#define CPU_SAVE_VERSION 12



/* MMU modes definitions */

#define MMU_MODE0_SUFFIX _kernel

#define MMU_MODE1_SUFFIX _user

target-i386/machine.c

+107 −108
Original line number Diff line number Diff line
@@ -171,14 +171,16 @@ static const VMStateInfo vmstate_fpreg_1_no_mmx = { 


static bool fpregs_is_0(void *opaque, int version_id)

{

    CPUX86State *env = opaque;

    X86CPU *cpu = opaque;

    CPUX86State *env = &cpu->env;



    return (env->fpregs_format_vmstate == 0);

}



static bool fpregs_is_1_mmx(void *opaque, int version_id)

{

    CPUX86State *env = opaque;

    X86CPU *cpu = opaque;

    CPUX86State *env = &cpu->env;

    int guess_mmx;



    guess_mmx = ((env->fptag_vmstate == 0xff) &&
@@ -188,7 +190,8 @@ static bool fpregs_is_1_mmx(void *opaque, int version_id) 


static bool fpregs_is_1_no_mmx(void *opaque, int version_id)

{

    CPUX86State *env = opaque;

    X86CPU *cpu = opaque;

    CPUX86State *env = &cpu->env;

    int guess_mmx;



    guess_mmx = ((env->fptag_vmstate == 0xff) &&
@@ -237,7 +240,8 @@ static const VMStateInfo vmstate_hack_uint64_as_uint32 = { 


static void cpu_pre_save(void *opaque)

{

    CPUX86State *env = opaque;

    X86CPU *cpu = opaque;

    CPUX86State *env = &cpu->env;

    int i;



    /* FPU */
@@ -252,7 +256,8 @@ static void cpu_pre_save(void *opaque) 


static int cpu_post_load(void *opaque, int version_id)

{

    CPUX86State *env = opaque;

    X86CPU *cpu = opaque;

    CPUX86State *env = &cpu->env;

    int i;



    /* XXX: restore FPU round state */
@@ -275,16 +280,16 @@ static int cpu_post_load(void *opaque, int version_id) 


static bool async_pf_msr_needed(void *opaque)

{

    CPUX86State *cpu = opaque;

    X86CPU *cpu = opaque;



    return cpu->async_pf_en_msr != 0;

    return cpu->env.async_pf_en_msr != 0;

}



static bool pv_eoi_msr_needed(void *opaque)

{

    CPUX86State *cpu = opaque;

    X86CPU *cpu = opaque;



    return cpu->pv_eoi_en_msr != 0;

    return cpu->env.pv_eoi_en_msr != 0;

}



static const VMStateDescription vmstate_async_pf_msr = {
@@ -293,7 +298,7 @@ static const VMStateDescription vmstate_async_pf_msr = { 
    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField []) {

        VMSTATE_UINT64(async_pf_en_msr, CPUX86State),

        VMSTATE_UINT64(env.async_pf_en_msr, X86CPU),

        VMSTATE_END_OF_LIST()

    }

};
@@ -304,14 +309,15 @@ static const VMStateDescription vmstate_pv_eoi_msr = { 
    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField []) {

        VMSTATE_UINT64(pv_eoi_en_msr, CPUX86State),

        VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU),

        VMSTATE_END_OF_LIST()

    }

};



static bool fpop_ip_dp_needed(void *opaque)

{

    CPUX86State *env = opaque;

    X86CPU *cpu = opaque;

    CPUX86State *env = &cpu->env;



    return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;

}
@@ -322,16 +328,17 @@ static const VMStateDescription vmstate_fpop_ip_dp = { 
    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField []) {

        VMSTATE_UINT16(fpop, CPUX86State),

        VMSTATE_UINT64(fpip, CPUX86State),

        VMSTATE_UINT64(fpdp, CPUX86State),

        VMSTATE_UINT16(env.fpop, X86CPU),

        VMSTATE_UINT64(env.fpip, X86CPU),

        VMSTATE_UINT64(env.fpdp, X86CPU),

        VMSTATE_END_OF_LIST()

    }

};



static bool tsc_adjust_needed(void *opaque)

{

    CPUX86State *env = opaque;

    X86CPU *cpu = opaque;

    CPUX86State *env = &cpu->env;



    return env->tsc_adjust != 0;

}
@@ -342,14 +349,15 @@ static const VMStateDescription vmstate_msr_tsc_adjust = { 
    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField[]) {

        VMSTATE_UINT64(tsc_adjust, CPUX86State),

        VMSTATE_UINT64(env.tsc_adjust, X86CPU),

        VMSTATE_END_OF_LIST()

    }

};



static bool tscdeadline_needed(void *opaque)

{

    CPUX86State *env = opaque;

    X86CPU *cpu = opaque;

    CPUX86State *env = &cpu->env;



    return env->tsc_deadline != 0;

}
@@ -360,14 +368,15 @@ static const VMStateDescription vmstate_msr_tscdeadline = { 
    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField []) {

        VMSTATE_UINT64(tsc_deadline, CPUX86State),

        VMSTATE_UINT64(env.tsc_deadline, X86CPU),

        VMSTATE_END_OF_LIST()

    }

};



static bool misc_enable_needed(void *opaque)

{

    CPUX86State *env = opaque;

    X86CPU *cpu = opaque;

    CPUX86State *env = &cpu->env;



    return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;

}
@@ -378,111 +387,111 @@ static const VMStateDescription vmstate_msr_ia32_misc_enable = { 
    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField []) {

        VMSTATE_UINT64(msr_ia32_misc_enable, CPUX86State),

        VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU),

        VMSTATE_END_OF_LIST()

    }

};



static const VMStateDescription vmstate_cpu = {

const VMStateDescription vmstate_x86_cpu = {

    .name = "cpu",

    .version_id = CPU_SAVE_VERSION,

    .version_id = 12,

    .minimum_version_id = 3,

    .minimum_version_id_old = 3,

    .pre_save = cpu_pre_save,

    .post_load = cpu_post_load,

    .fields      = (VMStateField []) {

        VMSTATE_UINTTL_ARRAY(regs, CPUX86State, CPU_NB_REGS),

        VMSTATE_UINTTL(eip, CPUX86State),

        VMSTATE_UINTTL(eflags, CPUX86State),

        VMSTATE_UINT32(hflags, CPUX86State),

        VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS),

        VMSTATE_UINTTL(env.eip, X86CPU),

        VMSTATE_UINTTL(env.eflags, X86CPU),

        VMSTATE_UINT32(env.hflags, X86CPU),

        /* FPU */

        VMSTATE_UINT16(fpuc, CPUX86State),

        VMSTATE_UINT16(fpus_vmstate, CPUX86State),

        VMSTATE_UINT16(fptag_vmstate, CPUX86State),

        VMSTATE_UINT16(fpregs_format_vmstate, CPUX86State),

        VMSTATE_FP_REGS(fpregs, CPUX86State, 8),



        VMSTATE_SEGMENT_ARRAY(segs, CPUX86State, 6),

        VMSTATE_SEGMENT(ldt, CPUX86State),

        VMSTATE_SEGMENT(tr, CPUX86State),

        VMSTATE_SEGMENT(gdt, CPUX86State),

        VMSTATE_SEGMENT(idt, CPUX86State),



        VMSTATE_UINT32(sysenter_cs, CPUX86State),

        VMSTATE_UINT16(env.fpuc, X86CPU),

        VMSTATE_UINT16(env.fpus_vmstate, X86CPU),

        VMSTATE_UINT16(env.fptag_vmstate, X86CPU),

        VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU),

        VMSTATE_FP_REGS(env.fpregs, X86CPU, 8),



        VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),

        VMSTATE_SEGMENT(env.ldt, X86CPU),

        VMSTATE_SEGMENT(env.tr, X86CPU),

        VMSTATE_SEGMENT(env.gdt, X86CPU),

        VMSTATE_SEGMENT(env.idt, X86CPU),



        VMSTATE_UINT32(env.sysenter_cs, X86CPU),

#ifdef TARGET_X86_64

        /* Hack: In v7 size changed from 32 to 64 bits on x86_64 */

        VMSTATE_HACK_UINT32(sysenter_esp, CPUX86State, less_than_7),

        VMSTATE_HACK_UINT32(sysenter_eip, CPUX86State, less_than_7),

        VMSTATE_UINTTL_V(sysenter_esp, CPUX86State, 7),

        VMSTATE_UINTTL_V(sysenter_eip, CPUX86State, 7),

        VMSTATE_HACK_UINT32(env.sysenter_esp, X86CPU, less_than_7),

        VMSTATE_HACK_UINT32(env.sysenter_eip, X86CPU, less_than_7),

        VMSTATE_UINTTL_V(env.sysenter_esp, X86CPU, 7),

        VMSTATE_UINTTL_V(env.sysenter_eip, X86CPU, 7),

#else

        VMSTATE_UINTTL(sysenter_esp, CPUX86State),

        VMSTATE_UINTTL(sysenter_eip, CPUX86State),

        VMSTATE_UINTTL(env.sysenter_esp, X86CPU),

        VMSTATE_UINTTL(env.sysenter_eip, X86CPU),

#endif



        VMSTATE_UINTTL(cr[0], CPUX86State),

        VMSTATE_UINTTL(cr[2], CPUX86State),

        VMSTATE_UINTTL(cr[3], CPUX86State),

        VMSTATE_UINTTL(cr[4], CPUX86State),

        VMSTATE_UINTTL_ARRAY(dr, CPUX86State, 8),

        VMSTATE_UINTTL(env.cr[0], X86CPU),

        VMSTATE_UINTTL(env.cr[2], X86CPU),

        VMSTATE_UINTTL(env.cr[3], X86CPU),

        VMSTATE_UINTTL(env.cr[4], X86CPU),

        VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),

        /* MMU */

        VMSTATE_INT32(a20_mask, CPUX86State),

        VMSTATE_INT32(env.a20_mask, X86CPU),

        /* XMM */

        VMSTATE_UINT32(mxcsr, CPUX86State),

        VMSTATE_XMM_REGS(xmm_regs, CPUX86State, CPU_NB_REGS),

        VMSTATE_UINT32(env.mxcsr, X86CPU),

        VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, CPU_NB_REGS),



#ifdef TARGET_X86_64

        VMSTATE_UINT64(efer, CPUX86State),

        VMSTATE_UINT64(star, CPUX86State),

        VMSTATE_UINT64(lstar, CPUX86State),

        VMSTATE_UINT64(cstar, CPUX86State),

        VMSTATE_UINT64(fmask, CPUX86State),

        VMSTATE_UINT64(kernelgsbase, CPUX86State),

        VMSTATE_UINT64(env.efer, X86CPU),

        VMSTATE_UINT64(env.star, X86CPU),

        VMSTATE_UINT64(env.lstar, X86CPU),

        VMSTATE_UINT64(env.cstar, X86CPU),

        VMSTATE_UINT64(env.fmask, X86CPU),

        VMSTATE_UINT64(env.kernelgsbase, X86CPU),

#endif

        VMSTATE_UINT32_V(smbase, CPUX86State, 4),



        VMSTATE_UINT64_V(pat, CPUX86State, 5),

        VMSTATE_UINT32_V(hflags2, CPUX86State, 5),



        VMSTATE_UINT32_TEST(halted, CPUX86State, version_is_5),

        VMSTATE_UINT64_V(vm_hsave, CPUX86State, 5),

        VMSTATE_UINT64_V(vm_vmcb, CPUX86State, 5),

        VMSTATE_UINT64_V(tsc_offset, CPUX86State, 5),

        VMSTATE_UINT64_V(intercept, CPUX86State, 5),

        VMSTATE_UINT16_V(intercept_cr_read, CPUX86State, 5),

        VMSTATE_UINT16_V(intercept_cr_write, CPUX86State, 5),

        VMSTATE_UINT16_V(intercept_dr_read, CPUX86State, 5),

        VMSTATE_UINT16_V(intercept_dr_write, CPUX86State, 5),

        VMSTATE_UINT32_V(intercept_exceptions, CPUX86State, 5),

        VMSTATE_UINT8_V(v_tpr, CPUX86State, 5),

        VMSTATE_UINT32_V(env.smbase, X86CPU, 4),



        VMSTATE_UINT64_V(env.pat, X86CPU, 5),

        VMSTATE_UINT32_V(env.hflags2, X86CPU, 5),



        VMSTATE_UINT32_TEST(env.halted, X86CPU, version_is_5),

        VMSTATE_UINT64_V(env.vm_hsave, X86CPU, 5),

        VMSTATE_UINT64_V(env.vm_vmcb, X86CPU, 5),

        VMSTATE_UINT64_V(env.tsc_offset, X86CPU, 5),

        VMSTATE_UINT64_V(env.intercept, X86CPU, 5),

        VMSTATE_UINT16_V(env.intercept_cr_read, X86CPU, 5),

        VMSTATE_UINT16_V(env.intercept_cr_write, X86CPU, 5),

        VMSTATE_UINT16_V(env.intercept_dr_read, X86CPU, 5),

        VMSTATE_UINT16_V(env.intercept_dr_write, X86CPU, 5),

        VMSTATE_UINT32_V(env.intercept_exceptions, X86CPU, 5),

        VMSTATE_UINT8_V(env.v_tpr, X86CPU, 5),

        /* MTRRs */

        VMSTATE_UINT64_ARRAY_V(mtrr_fixed, CPUX86State, 11, 8),

        VMSTATE_UINT64_V(mtrr_deftype, CPUX86State, 8),

        VMSTATE_MTRR_VARS(mtrr_var, CPUX86State, 8, 8),

        VMSTATE_UINT64_ARRAY_V(env.mtrr_fixed, X86CPU, 11, 8),

        VMSTATE_UINT64_V(env.mtrr_deftype, X86CPU, 8),

        VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, 8, 8),

        /* KVM-related states */

        VMSTATE_INT32_V(interrupt_injected, CPUX86State, 9),

        VMSTATE_UINT32_V(mp_state, CPUX86State, 9),

        VMSTATE_UINT64_V(tsc, CPUX86State, 9),

        VMSTATE_INT32_V(exception_injected, CPUX86State, 11),

        VMSTATE_UINT8_V(soft_interrupt, CPUX86State, 11),

        VMSTATE_UINT8_V(nmi_injected, CPUX86State, 11),

        VMSTATE_UINT8_V(nmi_pending, CPUX86State, 11),

        VMSTATE_UINT8_V(has_error_code, CPUX86State, 11),

        VMSTATE_UINT32_V(sipi_vector, CPUX86State, 11),

        VMSTATE_INT32_V(env.interrupt_injected, X86CPU, 9),

        VMSTATE_UINT32_V(env.mp_state, X86CPU, 9),

        VMSTATE_UINT64_V(env.tsc, X86CPU, 9),

        VMSTATE_INT32_V(env.exception_injected, X86CPU, 11),

        VMSTATE_UINT8_V(env.soft_interrupt, X86CPU, 11),

        VMSTATE_UINT8_V(env.nmi_injected, X86CPU, 11),

        VMSTATE_UINT8_V(env.nmi_pending, X86CPU, 11),

        VMSTATE_UINT8_V(env.has_error_code, X86CPU, 11),

        VMSTATE_UINT32_V(env.sipi_vector, X86CPU, 11),

        /* MCE */

        VMSTATE_UINT64_V(mcg_cap, CPUX86State, 10),

        VMSTATE_UINT64_V(mcg_status, CPUX86State, 10),

        VMSTATE_UINT64_V(mcg_ctl, CPUX86State, 10),

        VMSTATE_UINT64_ARRAY_V(mce_banks, CPUX86State, MCE_BANKS_DEF *4, 10),

        VMSTATE_UINT64_V(env.mcg_cap, X86CPU, 10),

        VMSTATE_UINT64_V(env.mcg_status, X86CPU, 10),

        VMSTATE_UINT64_V(env.mcg_ctl, X86CPU, 10),

        VMSTATE_UINT64_ARRAY_V(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4, 10),

        /* rdtscp */

        VMSTATE_UINT64_V(tsc_aux, CPUX86State, 11),

        VMSTATE_UINT64_V(env.tsc_aux, X86CPU, 11),

        /* KVM pvclock msr */

        VMSTATE_UINT64_V(system_time_msr, CPUX86State, 11),

        VMSTATE_UINT64_V(wall_clock_msr, CPUX86State, 11),

        VMSTATE_UINT64_V(env.system_time_msr, X86CPU, 11),

        VMSTATE_UINT64_V(env.wall_clock_msr, X86CPU, 11),

        /* XSAVE related fields */

        VMSTATE_UINT64_V(xcr0, CPUX86State, 12),

        VMSTATE_UINT64_V(xstate_bv, CPUX86State, 12),

        VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUX86State, CPU_NB_REGS, 12),

        VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),

        VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),

        VMSTATE_YMMH_REGS_VARS(env.ymmh_regs, X86CPU, CPU_NB_REGS, 12),

        VMSTATE_END_OF_LIST()

        /* The above list is not sorted /wrt version numbers, watch out! */

    },
@@ -510,13 +519,3 @@ static const VMStateDescription vmstate_cpu = { 
        }

    }

};
 


void cpu_save(QEMUFile *f, void *opaque)

{

    vmstate_save_state(f, &vmstate_cpu, opaque);

}



int cpu_load(QEMUFile *f, void *opaque, int version_id)

{

    return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);

}