Commit 20d6c731 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-3.2-part1' into staging 



RISC-V Changes for 3.2, Part 1

This pull request contains the first set of RISC-V patches I'd like to
target for the 3.2 development cycle.  It's really just a collection of
bug fixes with one major new feature: PCIe can now be attached to RISC-V
guests.

This has passed my usual test of booting the latest Linux RC into a
Fedora disk image on the virt machine.

# gpg: Signature made Fri 21 Dec 2018 16:01:29 GMT
# gpg:                using RSA key EF4CA1502CCBAB41
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>"
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-3.2-part1:
  MAINTAINERS: Mark RISC-V as Supported
  riscv/cpu: use device_class_set_parent_realize
  target/riscv/pmp.c: Fix pmp_decode_napot()
  sifive_uart: Implement interrupt pending register
  RISC-V: Enable second UART on sifive_e and sifive_u
  RISC-V: Fix PLIC pending bitfield reads
  RISC-V: Fix CLINT timecmp low 32-bit writes
  RISC-V: Add hartid and \n to interrupt logging
  sifive_u: Set 'clock-frequency' DT property for SiFive UART
  sifive_u: Add clock DT node for GEM ethernet
  riscv: Enable VGA and PCIE_VGA
  hw/riscv/virt: Connect the gpex PCIe
  hw/riscv/virt: Adjust memory layout spacing
  hw/riscv/virt: Increase the number of interrupts

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 1b3e8008 7b91ae7d

MAINTAINERS

+1 −1
Original line number Diff line number Diff line
@@ -262,7 +262,7 @@ M: Alistair Francis <Alistair.Francis@wdc.com> 
M: Sagar Karandikar <sagark@eecs.berkeley.edu>

M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

L: qemu-riscv@nongnu.org

S: Maintained

S: Supported

F: target/riscv/

F: hw/riscv/

F: include/hw/riscv/

default-configs/riscv32-softmmu.mak

+7 −1
Original line number Diff line number Diff line 
# Default configuration for riscv-softmmu



include pci.mak



CONFIG_SERIAL=y

CONFIG_VIRTIO_MMIO=y

include virtio.mak



CONFIG_CADENCE=y



CONFIG_PCI_GENERIC=y



CONFIG_VGA=y

CONFIG_VGA_PCI=y

default-configs/riscv64-softmmu.mak

+7 −1
Original line number Diff line number Diff line 
# Default configuration for riscv-softmmu



include pci.mak



CONFIG_SERIAL=y

CONFIG_VIRTIO_MMIO=y

include virtio.mak



CONFIG_CADENCE=y



CONFIG_PCI_GENERIC=y



CONFIG_VGA=y

CONFIG_VGA_PCI=y

hw/riscv/sifive_clint.c

+4 −4
Original line number Diff line number Diff line
@@ -146,15 +146,15 @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value, 
            error_report("clint: invalid timecmp hartid: %zu", hartid);

        } else if ((addr & 0x7) == 0) {

            /* timecmp_lo */

            uint64_t timecmp = env->timecmp;

            uint64_t timecmp_hi = env->timecmp >> 32;

            sifive_clint_write_timecmp(RISCV_CPU(cpu),

                timecmp << 32 | (value & 0xFFFFFFFF));

                timecmp_hi << 32 | (value & 0xFFFFFFFF));

            return;

        } else if ((addr & 0x7) == 4) {

            /* timecmp_hi */

            uint64_t timecmp = env->timecmp;

            uint64_t timecmp_lo = env->timecmp;

            sifive_clint_write_timecmp(RISCV_CPU(cpu),

                value << 32 | (timecmp & 0xFFFFFFFF));

                value << 32 | (timecmp_lo & 0xFFFFFFFF));

        } else {

            error_report("clint: invalid timecmp write: %08x", (uint32_t)addr);

        }

hw/riscv/sifive_e.c

+2 −3
Original line number Diff line number Diff line
@@ -192,9 +192,8 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) 
        memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);

    sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0",

        memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);

    /* sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,

        serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic),

                                       SIFIVE_E_UART1_IRQ)); */

    sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,

        serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));

    sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1",

        memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);

    sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1",