Commit 1b3e8008 authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20181226' into staging 



Host support for riscv64.
Dead code elimination pass.
Register allocation improvements.

# gpg: Signature made Tue 25 Dec 2018 20:52:34 GMT
# gpg:                using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20181226: (42 commits)
  tcg: Improve call argument loading
  tcg: Record register preferences during liveness
  tcg: Add TCG_OPF_BB_EXIT
  tcg: Split out more subroutines from liveness_pass_1
  tcg: Rename and adjust liveness_pass_1 helpers
  tcg: Reindent parts of liveness_pass_1
  tcg: Dump register preference info with liveness
  tcg: Improve register allocation for matching constraints
  tcg: Add output_pref to TCGOp
  tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi
  tcg: Add preferred_reg argument to temp_sync
  tcg: Add preferred_reg argument to temp_load
  tcg: Add preferred_reg argument to tcg_reg_alloc
  tcg: Add reachable_code_pass
  tcg: Reference count labels
  tcg: Add TCG_CALL_NO_RETURN
  tcg: Renumber TCG_CALL_* flags
  linux-user: Add safe_syscall for riscv64 host
  disas/microblaze: Remove unused REG_SP macro
  configure: Add support for building RISC-V host
  ...

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parents 9b2e891e 4250da10

MAINTAINERS

+11 −1
Original line number Diff line number Diff line
@@ -266,7 +266,8 @@ S: Maintained 
F: target/riscv/

F: hw/riscv/

F: include/hw/riscv/

F: disas/riscv.c

F: linux-user/host/riscv32/

F: linux-user/host/riscv64/



S390

M: Richard Henderson <rth@twiddle.net>
@@ -2172,6 +2173,15 @@ S: Odd Fixes 
F: tcg/ppc/

F: disas/ppc.c



RISC-V

M: Michael Clark <mjc@sifive.com>

M: Palmer Dabbelt <palmer@sifive.com>

M: Alistair Francis <Alistair.Francis@wdc.com>

L: qemu-riscv@nongnu.org

S: Maintained

F: tcg/riscv/

F: disas/riscv.c



S390 target

M: Richard Henderson <rth@twiddle.net>

S: Maintained

accel/tcg/user-exec.c

+75 −0
Original line number Diff line number Diff line
@@ -571,6 +571,81 @@ int cpu_signal_handler(int host_signum, void *pinfo, 
    return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);

}



#elif defined(__riscv)



int cpu_signal_handler(int host_signum, void *pinfo,

                       void *puc)

{

    siginfo_t *info = pinfo;

    ucontext_t *uc = puc;

    greg_t pc = uc->uc_mcontext.__gregs[REG_PC];

    uint32_t insn = *(uint32_t *)pc;

    int is_write = 0;



    /* Detect store by reading the instruction at the program

       counter. Note: we currently only generate 32-bit

       instructions so we thus only detect 32-bit stores */

    switch (((insn >> 0) & 0b11)) {

    case 3:

        switch (((insn >> 2) & 0b11111)) {

        case 8:

            switch (((insn >> 12) & 0b111)) {

            case 0: /* sb */

            case 1: /* sh */

            case 2: /* sw */

            case 3: /* sd */

            case 4: /* sq */

                is_write = 1;

                break;

            default:

                break;

            }

            break;

        case 9:

            switch (((insn >> 12) & 0b111)) {

            case 2: /* fsw */

            case 3: /* fsd */

            case 4: /* fsq */

                is_write = 1;

                break;

            default:

                break;

            }

            break;

        default:

            break;

        }

    }



    /* Check for compressed instructions */

    switch (((insn >> 13) & 0b111)) {

    case 7:

        switch (insn & 0b11) {

        case 0: /*c.sd */

        case 2: /* c.sdsp */

            is_write = 1;

            break;

        default:

            break;

        }

        break;

    case 6:

        switch (insn & 0b11) {

        case 0: /* c.sw */

        case 3: /* c.swsp */

            is_write = 1;

            break;

        default:

            break;

        }

        break;

    default:

        break;

    }



    return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);

}



#else



#error host CPU specific signal handler needed

configure

+10 −2
Original line number Diff line number Diff line
@@ -710,6 +710,12 @@ elif check_define __s390__ ; then 
  else

    cpu="s390"

  fi

elif check_define __riscv ; then

  if check_define _LP64 ; then

    cpu="riscv64"

  else

    cpu="riscv32"

  fi

elif check_define __arm__ ; then

  cpu="arm"

elif check_define __aarch64__ ; then
@@ -722,7 +728,7 @@ ARCH= 
# Normalise host CPU name and set ARCH.

# Note that this case should only have supported host CPUs, not guests.

case "$cpu" in

  ppc|ppc64|s390|s390x|sparc64|x32)

  ppc|ppc64|s390|s390x|sparc64|x32|riscv32|riscv64)

    cpu="$cpu"

    supported_cpu="yes"

    eval "cross_cc_${cpu}=\$host_cc"
@@ -6937,6 +6943,8 @@ elif test "$ARCH" = "x86_64" -o "$ARCH" = "x32" ; then 
  QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/i386 $QEMU_INCLUDES"

elif test "$ARCH" = "ppc64" ; then

  QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/ppc $QEMU_INCLUDES"

elif test "$ARCH" = "riscv32" -o "$ARCH" = "riscv64" ; then

  QEMU_INCLUDES="-I\$(SRC_PATH)/tcg/riscv $QEMU_INCLUDES"

else

  QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/\$(ARCH) $QEMU_INCLUDES"

fi
@@ -7433,7 +7441,7 @@ for i in $ARCH $TARGET_BASE_ARCH ; do 
  ppc*)

    disas_config "PPC"

  ;;

  riscv)

  riscv*)

    disas_config "RISCV"

  ;;

  s390*)

disas.c

+8 −2
Original line number Diff line number Diff line
@@ -522,8 +522,14 @@ void disas(FILE *out, void *code, unsigned long size) 
# ifdef _ARCH_PPC64

    s.info.cap_mode = CS_MODE_64;

# endif

#elif defined(__riscv__)

    print_insn = print_insn_riscv;

#elif defined(__riscv) && defined(CONFIG_RISCV_DIS)

#if defined(_ILP32) || (__riscv_xlen == 32)

    print_insn = print_insn_riscv32;

#elif defined(_LP64)

    print_insn = print_insn_riscv64;

#else

#error unsupported RISC-V ABI

#endif

#elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS)

    print_insn = print_insn_arm_a64;

    s.info.cap_arch = CS_ARCH_ARM64;

disas/microblaze.c

+0 −1
Original line number Diff line number Diff line
@@ -176,7 +176,6 @@ enum microblaze_instr_type { 
#define REG_TLBSX 36869 /* MMU: TLB Search Index reg */



/* alternate names for gen purpose regs */

#define REG_SP  1 /* stack pointer */

#define REG_ROSDP 2 /* read-only small data pointer */

#define REG_RWSDP 13 /* read-write small data pointer */