Commit 20b28ebc authored by Yongbok Kim's avatar Yongbok Kim Committed by Aleksandar Markovic
Browse files

target/mips: Add CP0 PWSize register 



Add PWSize register (CP0 Register 5, Select 7).

The PWSize register configures hardware page table walking for TLB
refills.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:

BDW  (37..32) Base Directory index width (MIPS64 only)
GDW  (29..24) Global Directory index width
UDW  (23..18) Upper Directory index width
MDW  (17..12) Middle Directory index width
PTW  (11..6 ) Page Table index width
PTEW ( 5..0 ) Left shift applied to the Page Table index

Reviewed-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: default avatarYongbok Kim <yongbok.kim@mips.com>
Signed-off-by: default avatarAleksandar Markovic <amarkovic@wavecomp.com>
parent fa75ad14

target/mips/cpu.h

+10 −0
Original line number Diff line number Diff line
@@ -432,6 +432,16 @@ struct CPUMIPSState { 
#define CP0PF_PTW  6     /* 11..6  */

#define CP0PF_PTEW 0     /*  5..0  */

#endif

    target_ulong CP0_PWSize;

#if defined(TARGET_MIPS64)

#define CP0PS_BDW  32    /* 37..32 */

#endif

#define CP0PS_PS   30

#define CP0PS_GDW  24    /* 29..24 */

#define CP0PS_UDW  18    /* 23..18 */

#define CP0PS_MDW  12    /* 17..12 */

#define CP0PS_PTW  6     /* 11..6  */

#define CP0PS_PTEW 0     /*  5..0  */

/*

 * CP0 Register 6

 */

target/mips/helper.h

+1 −0
Original line number Diff line number Diff line
@@ -121,6 +121,7 @@ DEF_HELPER_2(mtc0_segctl0, void, env, tl) 
DEF_HELPER_2(mtc0_segctl1, void, env, tl)

DEF_HELPER_2(mtc0_segctl2, void, env, tl)

DEF_HELPER_2(mtc0_pwfield, void, env, tl)

DEF_HELPER_2(mtc0_pwsize, void, env, tl)

DEF_HELPER_2(mtc0_wired, void, env, tl)

DEF_HELPER_2(mtc0_srsconf0, void, env, tl)

DEF_HELPER_2(mtc0_srsconf1, void, env, tl)

target/mips/machine.c

+3 −2
Original line number Diff line number Diff line
@@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb = { 


const VMStateDescription vmstate_mips_cpu = {

    .name = "cpu",

    .version_id = 13,

    .minimum_version_id = 13,

    .version_id = 14,

    .minimum_version_id = 14,

    .post_load = cpu_post_load,

    .fields = (VMStateField[]) {

        /* Active TC */
@@ -258,6 +258,7 @@ const VMStateDescription vmstate_mips_cpu = { 
        VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU),

        VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU),

        VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU),

        VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU),

        VMSTATE_INT32(env.CP0_Wired, MIPSCPU),

        VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),

        VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),

target/mips/op_helper.c

+9 −0
Original line number Diff line number Diff line
@@ -1507,6 +1507,15 @@ void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1) 
#endif

}



void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)

{

#if defined(TARGET_MIPS64)

    env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL;

#else

    env->CP0_PWSize = arg1 & 0x3FFFFFFF;

#endif

}



void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)

{

    if (env->insn_flags & ISA_MIPS32R6) {

target/mips/translate.c

+20 −0
Original line number Diff line number Diff line
@@ -6111,6 +6111,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) 
            gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));

            rn = "PWField";

            break;

        case 7:

            check_pw(ctx);

            gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize));

            rn = "PWSize";

            break;

        default:

            goto cp0_unimplemented;

        }
@@ -6822,6 +6827,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) 
            gen_helper_mtc0_pwfield(cpu_env, arg);

            rn = "PWField";

            break;

        case 7:

            check_pw(ctx);

            gen_helper_mtc0_pwsize(cpu_env, arg);

            rn = "PWSize";

            break;

        default:

            goto cp0_unimplemented;

        }
@@ -7542,6 +7552,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) 
            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField));

            rn = "PWField";

            break;

        case 7:

            check_pw(ctx);

            tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize));

            rn = "PWSize";

            break;

        default:

            goto cp0_unimplemented;

        }
@@ -8235,6 +8250,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) 
            gen_helper_mtc0_pwfield(cpu_env, arg);

            rn = "PWField";

            break;

        case 7:

            check_pw(ctx);

            gen_helper_mtc0_pwsize(cpu_env, arg);

            rn = "PWSize";

            break;

        default:

            goto cp0_unimplemented;

        }